參數(shù)資料
型號: TE28F800CEB120
廠商: Intel Corp.
英文描述: 8-MBIT (512K X 16, 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 8兆位(為512k × 16,1024K × 8)SmartVoltage啟動塊閃存系列
文件頁數(shù): 32/55頁
文件大?。?/td> 638K
代理商: TE28F800CEB120
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
32
SEE NEW DESIGN RECOMMENDATIONS
4.4
DC Characteristics
—Commercial
(Continued)
Prod
BV-60
BV-80
BV-120
Sym
Parameter
V
CC
3.3 ± 0.3 V
5 V ± 10%
Unit
Test Conditions
Note
Min
Max
Min
Max
V
ID
A
9
Intelligent Identifier
Voltage
11.4
12.6
11.4
12.6
V
V
IL
Input Low Voltage
–0.5
0.8
–0.5
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+
0.5V
2.0
V
CC
+
0.5V
V
V
OL
Output Low Voltage
0.45
0.45
V
V
CC
= V
CC
Min
I
OL
= 5.8 mA
V
CC
= V
CC
Min
I
OH
= –2.5 mA
V
CC
= V
CC
Min
I
OH
= –2.5 mA
V
CC
= V
CC
Min
I
OH
= –100
μ
A
V
OH
1
Output High Voltage (TTL)
2.4
2.4
V
V
OH
2
Output High Voltage (CMOS)
0.85
×
V
CC
0.85
×
V
CC
V
V
CC
0.4V
V
CC
0.4V
V
V
PPLK
V
PP
Lock-Out Voltage
3
0.0
1.5
0.0
1.5
V
Total Write Protect
V
PPH
1 V
PP
(Prog/Erase Operations)
4.5
5.5
4.5
5.5
V
V
PP
at 5 V
V
PPH
2 V
PP
(Prog/Erase Operations)
11.4
12.6
11.4
12.6
V
V
PP
at 12 V
V
LKO
V
CC
Erase/Prog Lock Voltage
8
2.0
2.0
V
V
HH
RP# Unlock Voltage
11.4
12.6
11.4
12.6
V
Boot Block Unlock
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
CC
= 5.0 V, T = +25 °C. These currents are valid for all
product versions (packages and speeds).
2. I
CCES
is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of
I
CCES
and I
CCR
.
3. Block erases and word/byte programs are inhibited when V
PP
= V
PPLK
, and not guaranteed in the range between V
PPH
1 and
V
PPLK
.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I
CCR
to less than 1 mA typical, in static operation.
6. CMOS Inputs are either V
CC
± 0.2 V or GND ± 0.2 V. TTL Inputs are either V
IL
or V
IH
.
7. For the 28F002B, address pin A
10
follows the C
OUT
capacitance numbers.
8. For all BV/CV parts, V
LKO
= 2.0 V for both 3.3 V and 5 V operations.
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