參數資料
型號: TE28F256J3C-150
廠商: Intel Corp.
英文描述: Intel StrataFlash Memory (J3)
中文描述: 英特爾StrataFlash存儲器(J3)
文件頁數: 35/72頁
文件大?。?/td> 905K
代理商: TE28F256J3C-150
256-Mbit J3 (x8/x16)
Datasheet
35
9.2
Device Commands
When the V
PEN
voltage
V
PENLK
, only read operations from the Status Register, CFI, identifier
codes, or blocks are enabled. Placing V
PENH
on V
PEN
additionally enables block erase, program,
and lock-bit configuration operations. Device operations are selected by writing specific
commands into the CUI.
Table 14, “Command Bus-Cycle Definitions” on page 35
defines these
commands.
Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)
Command
Scalable or
Basic
Command
Set
(2)
Bus
Cycles
Req’d.
First Bus Cycle
Second Bus Cycle
Notes
Oper
(3)
Addr
(4)
Data
(5,6)
Oper
(3)
Addr
(4)
Data
(5,6)
Read Array
SCS/BCS
1
Write
X
0xFF
1
Read Identifier Codes
SCS/BCS
2
Write
X
0X90
Read
IA
ID
1,7
Read Query
SCS
2
Write
X
0x98
Read
QA
QD
1
Read Status Register
SCS/BCS
2
Write
X
0x70
Read
X
SRD
1,8
Clear Status Register
SCS/BCS
1
Write
X
0x50
1
Write to Buffer
SCS/BCS
> 2
Write
BA
0xE8
Write
BA
N
1,9, 10,
11
Word/Byte Program
SCS/BCS
2
Write
X
0x40 or
0x10
Write
PA
PD
1,12,13
Block Erase
SCS/BCS
2
Write
BA
0x20
Write
BA
0xD0
1,11,12
Block Erase, Program
Suspend
SCS/BCS
1
Write
X
0xB0
1,12,14
Block Erase, Program
Resume
SCS/BCS
1
Write
X
0xD0
1,12
Configuration
SCS
2
Write
X
0xB8
Write
X
CC
1
Set Block Lock-Bit
SCS
2
Write
X
0x60
Write
BA
0x01
1
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