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參數(shù)資料
| 型號： | TE28F004BX-T80 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | Series RR3130 round rocker switches have an ergonomic euro design and panel mounting |
| 中文描述： | 512K X 8 FLASH 12V PROM, 80 ns, PDSO40 |
| 封裝： | 20 X 10 MM, TSOP-40 |
| 文件頁數(shù)： | 56/58頁 |
| 文件大小： | 920K |
| 代理商： | TE28F004BX-T80 |
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
50
3UHOLPLQDU\
0580_E3
Figure 12. Block Erase Flowchart
Start
Write 20H
Write D0H and
Block Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last write operation to reset device to read array mode.
Bus Operation
Standby
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
No
Yes
Suspend Erase
Suspend
Erase Loop
1
0
Standby
Command
Erase Setup
Erase Confirm
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = V
PP
Low Detect
Check SR.4,5
Both 1 = Command Sequence
Error
Read Status Register
Data (See Above)
V
PP
Range Error
Command Sequence
Error
Block Erase
Successful
SR.3 =
SR.4,5 =
1
0
1
0
Block Erase Error
SR.5 =
1
0
Attempted Erase of
Locked Block - Aborted
SR.1 =
1
0
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby
Check SR.5
1 = Block Erase Error
Standby
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
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