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參數(shù)資料
| 型號： | TE28F004BEB120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 512K X 8 FLASH 5V PROM, PDSO40 |
| 封裝： | 20 X 10 MM, TSOP-40 |
| 文件頁數(shù)： | 14/58頁 |
| 文件大?。?/td> | 920K |
| 代理商： | TE28F004BEB120 |
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28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8
3UHOLPLQDU\
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
2. X must be V
IL
, V
IH
for control pins and addresses.
3. See DC Characteristicsfor V
PPLK
, V
PP1
, V
PP2
, V
PP3
, V
PP4
voltages.
4. Manufacturer and device codes may also be accessed in read identifier mode (A
1
–A
21
= 0). See
Table 5
.
5. Refer to
Table 6
for valid D
IN
during a write operation.
6. To program or erase the lockable blocks, hold WP# at V
IH
.
7. RP# must be at GND
±
0.2 V to meet the maximum deep power-down current specified.
3.1.1
Read
The flash memory has four read modes available: read array, read identifier, read status and read
query. These modes are accessible independent of the V
PP
voltage. The appropriate Read Mode
command must be issued to the CUI to enter the corresponding mode. Upon initial device power
-
up or after exit from reset, the device automatically defaults to read array mode.
CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection
control; when active it enables the flash memory device. OE# is the data output control and it
drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at
V
IH
.
Figure 7
illustrates a read cycle.
3.1.2
Output Disable
With OE# at a logic
-
high level (V
IH
), the device outputs are disabled. Output pins are placed in a
high
-
impedance state.
3.1.3
Standby
Deselecting the device by bringing CE# to a logic
-
high level (V
IH
) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during program or erase operation, the device continues to consume active power until
the program or erase operation is complete.
3.1.4
Deep Power-Down / Reset
From read mode, RP# at V
IL
for time t
PLPH
deselects the memory, places output drivers in a high
-
impedance state, and turns off all internal circuits. After return from reset, a time t
PHQV
is required
until the initial read access outputs are valid. A delay (t
PHWL
or t
PHEL
) is required after return from
reset before a write can be initiated. After this wake
-
up interval, normal operation is restored. The
CUI resets to read array mode, and the status register is set to 80H. This case is shown in
Figure 9A
.
Table 3. Bus Operations
(1)
Mode
Note
RP#
CE#
OE#
WE#
DQ
0–7
DQ
8–15
Read (Array, Status, or Identifier)
2–4
V
IH
V
IL
V
IL
V
IH
D
OUT
D
OUT
Output Disable
2
V
IH
V
IL
V
IH
V
IH
High Z
High Z
Standby
2
V
IH
V
IH
X
X
High Z
High Z
Reset
2, 7
V
IL
X
X
X
High Z
High Z
Write
2, 5–7
V
IH
V
IL
V
IH
V
IL
D
IN
D
IN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TE28F004BET120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| TE28F004BVB80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| TE28F004BVT80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| TE28F004BX-B80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| TE28F004BX-B90 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
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