參數(shù)資料
型號(hào)： TDGL003
廠商： Microchip Technology
文件頁(yè)數(shù)： 5/214頁(yè)
文件大?。?/td> 0K
描述： BOARD DEV CHIPKIT MAX32
標(biāo)準(zhǔn)包裝： 1
系列： PIC® 32MX
類型： MCU
適用于相關(guān)產(chǎn)品： MPLAB?，Arduino? Mega
所含物品： 板
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PIC32MX3XX/4XX
DS61143H-page 102
2011 Microchip Technology Inc.
12.1
Parallel I/O (PIO) Ports
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a data direction or tri-state control register that
determines whether a digital pin is an input or an out-
put. Setting a TRISx register bit = 1 configures the cor-
responding I/O pin as an input; setting a TRISx register
bit = 0 configures the corresponding I/O pin as an out-
put. All port I/O pins are defined as inputs after a device
Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx latch
register
reads
the
last
value
written
to
the
corresponding port or latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
12.1.2
DIGITAL INPUTS
Pins are configured as digital inputs by setting the cor-
responding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
Several digital pins share functionality with analog
inputs and default to the analog inputs at POR. Setting
the corresponding bit in the AD1PCFG register = 1
enables the pin as a digital pin.
The maximum input voltage allowed on the input pins
is the same as the maximum VIH specification. Refer to
specification details.
12.1.3
ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and Comparator modules. Setting the cor-
responding bits in the AD1PCFG register = 0 enables
the pin as an analog input pin and must have the corre-
sponding TRIS bit set = 1 (input). If the TRIS bit is
cleared = 0 (output), the digital output level (VOH or
VOL) will be converted. Any time a port I/O pin is config-
ured as analog, its digital input is disabled and the cor-
responding PORTx register bit will read ‘0’. The
AD1PCFG Register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
12.1.4
DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the cor-
responding TRIS register bits = 0. When configured as
digital outputs, these pins are CMOS drivers or can be
configured as open drain outputs by setting the corre-
sponding bits in the ODCx Open-Drain Configuration
register.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired 5V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See the “Pin Diagrams” section for the available pins
and their functionality.
12.1.5
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the Comparator Reference mod-
ule to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
12.1.6
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
(CNx) allows devices to generate interrupt requests in
response to change of state on selected pin.
Each CNx pin also has a weak pull-up, which acts as a
current source connected to the pin. The pull-ups are
enabled by setting corresponding bit in CNPUE register.
Note:
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions as compared to the tra-
ditional read-modify-write method shown
below:
PORTC ^= 0x0001;
Note:
Analog levels on any pin that is defined as
a digital input (including the ANx pins)
may cause the input buffer to consume
current that exceeds the device specifica-
tions.
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