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參數(shù)資料
| 型號(hào)： | TDF8704T/4-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 102K |
| 代理商： | TDF8704T/4-T |
June 1994
9
Philips Semiconductors
Product specication
8-bit high-speed analog-to-digital converter
TDF8704
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must be less than 1 ns.
2. Full-scale sine wave (fi = 4.43 MHz; fclk = 50 MHz).
3. Determined by beat frequency method on a reconstructed sine wave signal for no missing codes and no glitches.
4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period. The
calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB
× 6.02 + 1.76 dB.
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
7. Measurement taken using video analyser VM700A.
8. Output data acquisition: the output data is available after the maximum delay time of td.
Timing (note 8; see Figs 5 and 7; fclk = 50 MHz)
tds
sampling delay time
2ns
th
output hold time
5
ns
td
output delay time
12
15
ns
3-state output delay times (see Figs 6 and 7)
tdZH
enable HIGH
610
ns
tdZL
enable LOW
12
16
ns
tdHZ
disable HIGH
50
54
ns
tdLZ
disable LOW
10
14
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.3
Influence of Tamb on VI(T) and VI(B) under
5 V supply.
handbook, halfpage
60
3.49
3.43
3.45
3.47
MBD868
1.29
1.23
1.25
1.27
V I (T)
(V)
VI (B)
(V)
20
60
100
T
( C)
o
0.1 mV/K
0.05 mV/K
VI (T)
VI (B)
amb
Fig.4
Influence of supply voltage on VI(T) and
VI(B) under Tamb = 25 °C.
andbook, halfpage
4.25
4.75
5.75
3.44
3.38
3.40
3.42
MSA689
5.25
1.28
1.22
1.24
1.26
V I (T)
(V)
V I (B)
(V)
17 mV/V
7 mV/V
V
(V)
CC
VI (T)
V I (B)
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