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參數(shù)資料
| 型號： | TDCS6440G |
| 廠商： | Lineage Power |
| 英文描述： | SONET/SDH 40 Gbits/s Cross Connect( SONET/SDH 40G位/秒交叉連接器件) |
| 中文描述： | SONET / SDH的40 Gb /秒交叉連接設(shè)備（SONET / SDH的40G的位/秒交叉連接器件） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 125K |
| 代理商： | TDCS6440G |
Product Brief
September 2000
TDCS6440G SONET/SDH
40 Gbits/s Cross Connect
Features
I
Versatile IC which supports an aggregate band-
width of 40 Gbits/s.
I
Supports flexible 64-port STS-12 data links.
I
Supports full nonblocking fabric with switching
granularity of STS-1/STM-1.
I
Support for line/path switching.
I
Supports any valid mix of STS-1 and concatenated
payloads from STS-3c to STS-192c.
I
Provides a standard 5-pin P1149.1 JTAG port with
memory BIST scan, and boundary scan.
I
Low-power 1.5 V operation with 3.3 V inputs and
outputs.
I
Configurable on-chip TSI block for switching of
STS-1s.
I
On-chip connection memory for flexible configura-
tion of working connections and protect connec-
tions for each STS-1.
I
792 LBGA package.
I
–40
°
C to +85 °C industrial temperature range.
Interface
I
Provides 64 STS-12 interfaces which can be used
as sixteen STS-48 interfaces or as four STS-192
interfaces.
I
Robust receiver interface capable of handling
STS-12 streams having combined static- and
dynamic-frame offsets of up to 24 bytes without
creating traffic disruption.
I
Frames to and performs integrity check on each
STS-12 interface.
I
Each STS-12 input interface consists of an LVDS
data input with integral clock and data recovery
(CDR).
I
Each STS-12 output interface consists of an LVDS
output.
I
Ability to insert on an AIS-L or pass-through when
an LOF condition occurs.
I
Interfaces have A1/A2 framing, link trace, parity,
and a communications link.
Cross Connect
I
Supports up to 768 STS-1 time slots.
I
64 input channels and 64 output channels.
I
Each input time slot can be connected to any/all
output time slots.
I
Each output time slot can be connected to all the
input time slot or be assigned AIS-P or UNEQ-P
I
Fully programmable and nonblocking cross con-
nect.
I
Supports drop-and-continue and full broadcast
capabilities.
I
Ability to insert path AIS and UNEQ indications on
any STS-1 under software control.
Protection Switching
I
Supports 1 + 1, 1:1, 1:N, UPSR, and BLSR protec-
tion mechanisms with four-connection memory.
I
Separate line and path protection mechanisms.
I
Supports equipment protection switching.
I
On-chip working/protected memory paths for easy
switch configurations.
Microprocessor Interface
I
Microprocessor interface supports both synchro-
nous and asynchronous operations.
I
16-bit wide data bus interface and 13-bit wide
address bus.
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