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參數(shù)資料
| 型號(hào)： | TDC1049 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 9-Bit, 30 Msps High-Speed A/D Converter(9位,30Msps 高速A/D轉(zhuǎn)換器) |
| 中文描述： | 9位，30 Msps的高速A / D轉(zhuǎn)換器（9位，30Msps高速的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大小： | 118K |
| 代理商： | TDC1049 |
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PRODUCT SPECIFICATION
TDC1049
14
Mechanical Dimensions
(continued)
68 Lead LCC
LID
A1
A
B1
B3
L3
PLANE 1
PLANE 2
DETAIL "A"
(j) x 45
°
INDEX CORNER
DETAIL "A"
See Note 1
(h) x 45
°
3 plcs
4
D2
D1
L2
L1
e
E
D
E3
E2
E1
D3
(j) x 45
°
4
A
A1
B1
B3
D/E
.082
.071
.022
.006
.938
.110
.093
.028
.022
.962
2.08
1.83
.560
.150
23.82
2.79
2.39
.710
.560
24.43
Symbol
Inches
Min.
Max.
Min.
Max.
Millimeters
Notes
3, 6
3, 6
2
2,5
D1/E1
D2/E2
e
h
j
L1
L2
L3
ND/NE
N
.800 BSC
.400 BSC
.050 BSC
.040 BSC
.020 BSC
.045
20.32 BSC
10.16 BSC
1.27 BSC
1.02 BSC
.510 BSC
1.14
4
4
.003
.015
.080
.380
5
.075
.095
1.91
2.41
.055
1.40
17
68
17
68
1
Notes:
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown on
planes 1 and 2. Plane 1 terminal 1 identification may be an extension
of the length of the metallized terminal which shall not be wider than
the B1 dimension.
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features (e.g.,
lid, castellations, terminals, thermal pads, etc.).
3. Dimension "A" controls the overall package thickness. The maximum
"A" dimension is the package height before being solder dipped.
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three dimensional
space traversing all of the ceramic layers in which a castellation was
designed. Dimension "B3" maximum and "L3" maximum define the
maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to
solder dripping.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
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