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參數(shù)資料
| 型號： | TDC1047 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 7-Bit, 20 Msps Monolithic Video A/D Converter(7位,20Msps 單片視頻A/D轉(zhuǎn)換器) |
| 中文描述： | 7位，20 Msps的單片視頻A / D轉(zhuǎn)換（7位，20Msps單片視頻的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 74K |
| 代理商： | TDC1047 |
TDC1047
PRODUCT SPECIFICATION
2
Functional Description
General Information
The TDC1047 has three functional sections: a comparator
array, encoding logic, and output latches. The comparator
array compares the input signal with 127 reference voltages
to produce an N-of-127 code (sometimes referred to as a
“thermometer” code, as all the comparators referred to
voltages more positive than the input signal will be off, and
those referred to voltages more negative than the input signal
will be on). The encoding logic converts the N-of-127 code
into binary or offset two’s complement coding, and can
invert either output code. This coding function is controlled
by DC signals on pins NMINV and NLINV. The output latch
holds the output constant between updates.
Power
The TDC1047 operates from two supply voltages, +5.0V
and -5.2V. The return for I
CC
+5.0V supply, is D
GND
. The return for I
drawn from the -5.2V supply, is A
ground pins must be connected.
, the current drawn from the
EE
, the current
GND
. All power and
Reference
The TDC1047 converts analog signals in the range
V
RB
￡
V
IN
￡
V
RT
into digital form. V
applied to the pin at the bottom of the reference resistor
chain) and V
RT
(the voltage applied to the pin at the top of
the reference resistor chain) should be between +0.1V and -
1.1V. V
RT
should be more positive than V
range. The voltage applied across the reference resistor chain
(V
RT
–V
RB
) must be between 0.8V and 1.2V. The nominal
voltages are V
RT
= 0.00V and V
may be varied dynamically up to 7MHz. Due to variation in
the reference currents with clock and input signals, R
R
B
should be low-impedance-to-ground points. For circuits
in which the reference is not varied, a bypass capacitor to
ground is recommended. If the reference inputs are exercised
dynamically as in an Automatic Gain Control (AGC) circuit,
a low-impedance reference source is recommended.
RB
(the voltage
RB
within that
RB
= -1.00V. These voltages
T
and
Controls
Two function control pins, NMINV and NLINV are
provided. These controls are for DC (i.e., steady state) use.
They permit the output coding to be either straight binary or
offset two’s complement, in either true or inverted sense,
according to the Output Coding Table. These pins are active
LOW as signified by the prefix “N” in the signal name. They
may be tied to V
CC
for a Logic 1 and D
GND
for a Logic 0.
Convert
The TDC1047 requires a CONVert (CONV) signal. A
sample is taken (the comparators are latched) within the
Sampling Time Offset (t
STO
pin. The 127 to 7 encoding is performed on the falling edge
of the CONV signal. The coded result is transferred to the
output latches on the next rising edge. The outputs hold the
previous data a minimum time (t
the CONV signal. This permits the previous conversion
result to be acquired by external circuitry at that rising edge,
i.e., data for sample N is acquired by the external circuitry
while the TDC1047 is taking input sample N+2.
) of a rising edge on the CONV
HO
) after the rising edge of
Analog Input
The TDC1047 uses strobed latching comparators which
cause the input impedance to vary with the signal level, as
comparator input transistors are cutoff or become active.
For optimal performance, both V
the source impedance of the driving circuit must be less than
30 Ohms. The input signal will not damage the TDC1047 if
it remains within the range of V
signal is between the V
RT
and V
will be a binary number between 0 and 127 inclusive.
A signal outside this range will indicate either full-scale
positive or full-scale negative, depending on whether the
signal is off-scale in the positive or negative direction.
IN
pins must be used and
EE
RB
to + 0.5V. If the input
references, the output
Outputs
The outputs of the TDC1047 are TTL compatible, and
capable of driving four low-power Schottky TTL (54/74 LS)
unit loads or the equivalent. The outputs hold the previous
data a minimum time (t
HO
) after the rising edge of the
CONV signal.
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
V
IN
R
T
A
GND
D
GND
NMINV
(MSB) D
1
D
2
D
3
D
4
V
CC
V
EE
A
GND
24
23
22
21
20
19
18
17
16
15
14
13
V
IN
R
B
A
GND
D
GND
CONV
D
7
(LSB)
D
6
D
5
V
CC
NLINV
V
EE
A
GND
24 Lead Ceramic DIP
65-1047-02
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