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參數(shù)資料
| 型號： | TDC1046 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 6-Bit, 25 Msps Monolithic Video A/D Converter(6位,25Msps 單片視頻A/D轉(zhuǎn)換器) |
| 中文描述： | 6位，25 Msps的單片視頻A / D轉(zhuǎn)換器（6位，25Msps時單片視頻的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 73K |
| 代理商： | TDC1046 |
TDC1046
PRODUCT SPECIFICATION
2
Functional Description
General Information
The TDC1046 has three functional sections: a comparator
array, encoding logic, and output latches. The comparator
array compares the input signal with 63 reference voltages
to produce an N-of-63 code (sometimes referred to as a
“thermometer” code, as all the comparators referred to
voltages more positive than the input signal will be off, and
those referred to voltages more negative than the input signal
will be on). The encoding logic converts the N-of-63 code
into binary or offset two’s complement coding, and can
invert either output code. This coding function is controlled
by DC signals on pins NMINV and NLINV. The output latch
holds the output constant between updates.
Power
The TDC1046 operates from two supply voltages, +5.0V
and -5.2V. The return for I
CC
+5.0V supply, is D
GND
. The return for I
drawn from the -5.2V supply, is A
ground pins must be connected.
, the current drawn from the
EE
, the current
GND
. All power and
Reference
The TDC1046 converts analog signals in the range
V
RB
￡
V
IN
￡
V
RT
into digital form. V
applied to R
B
at the bottom of the reference resistor chain)
and V
RT
(the voltage applied to R
resistor chain) should be between +0.1V and -1.1V. V
should be more positive than V
voltage applied across the reference resistor chain
(V
RT
–V
RB
) must be between 0.8V and 1.2V. The nominal
voltages are V
RT
= 0.00V and V
may be varied dynamically up to 12.5MHz. Due to variation
in the reference currents with clock and input signals, R
R
B
should be low-impedance-to-ground points. For circuits
in which the reference is not varied, a bypass capacitor to
ground is recommended. If the reference inputs are exercised
dynamically (as in an Automatic Gain Control circuit), a
low-impedance reference source is required.
RB
(the voltage
T
at the top of the reference
RT
RB
within that range. The
RG
= -1.00V. These voltages
T
and
Controls
Two function control pins, NMINV and NLINV are pro-
vided. These controls are for DC (i.e., steady states use. They
permit the output coding to be either straight binary or offset
two’s complement, in either true or inverted sense, according
to the Output Coding Table. These pins are active LOW as
signified by the prefix “N” in the signal name. They may be
tied to V
CC
for a logic “1” and D
GND
for a logic “0.”
Convert
The TDC1046 requires a CONVert (CONV) signal. A
sample is taken (the comparators are latched) within 5ns
after a rising edge on the CONV pin. This time is t
pling Time Offset. The 63 to 6 encoding is performed on the
falling edge of the CONV signal. The coded result is trans-
ferred to the output latches on the next rising edge. The out-
puts hold the previous data a minimum time (t
rising edge of the CONV signal.
STO
. Sam-
HO
) after the
Analog Input
The TDC1046 uses strobed latching comparators which
cause the input impedance to vary with the signal level, as
comparator input transistors are cut-off or become active.
For optimal performance, the source impedance of the
driving circuit must be less than 50
not damage the TDC1046 if it remains within the range of
V
EE
to +0.5V If the input signal is at a voltage between V
and V
RB
, the output will be a binary number between
0 and 63 inclusive. A signal outside this range will indicate
either full-scale positive or full-scale negative, depending on
whether the signal is off-scale in the positive or negative
direction.
W
. The input signal will
RT
Outputs
The outputs of the TDC1046 are TTL compatible, and
capable of driving four low-power Schottky TTL (54/74 LS)
unit loads or the equivalent. The outputs hold the previous
data a minimum time (t
HO
) after the rising edge of the
CONV signal. Data is guaranteed to be valid after a
maximum delay time (t
D
) after the rising edge of CONV.
For optimum performance, 2.2 K
ommended.
W
pull-up resistors are rec-
Pin Assignments
1
2
3
4
5
6
7
8
9
V
IN
R
T
D
GND
NMINV
(MSB) D
1
D
2
D
3
V
CC
V
EE
18
17
16
15
14
13
12
11
10
R
B
A
GND
D
GND
CONV
D
6
(LSB)
D
5
D
4
NLINV
V
CC
Ceramic DIP
65-1046-02
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