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參數資料
| 型號： | TDC1044AB9C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Monolithic Video A/D Converter 4-Bit, 25 Msps |
| 中文描述： | 1-CH 4-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數： | 2/16頁 |
| 文件大?。?/td> | 79K |
| 代理商： | TDC1044AB9C |
TDC1044A
PRODUCT SPECIFICATION
2
Functional Description
General Information
The TDC1044A has three functional sections: a comparator
array, encoding logic, and an output register. The comparator
array compares the input signal with 15 reference voltages to
produce an N-of-15 thermometer code. All the comparators
referred to voltages more positive than the input signal will
be off, and those referred to voltages more negative than the
input signal will be on. Encoding logic converts the N-of-15
code into binary or two’s complement coding and can invert
either output code. This coding function is controlled by DC
signals on pins NMINV and NLINV. The output register
holds the output constant between updates.
Power
The TDC1044A operates from two power supply voltages,
+5.0V and -5.2V. The return for I
the +5.0V supply) is D
GND
. The return for I
drawn from the -5.2V supply) is A
ground pins must be connected.
CC
(the current drawn from
EE
(the current
GND
. All power and
Reference
The TDC1044A converts analog signals in the range
V
RB
￡
V
IN
￡
V
RB
into digital form. V
applied to R
B
at the bottom of the reference resistor chain)
and V
RT
(the voltage applied to R
ence resistor chain) should be between +0.1V and -1.1V.
V
RT
should be more positive than V
The voltage applied across the reference resistor chain
(V
RT
– V
RB
) must be between 0.4V and 1.3V.
RB
(the voltage
B
at the top of the refer-
RB
within that range.
Nominal voltages are V
voltages may be varied dynamically up to 10MHz. Due to
slight variation in the reference currents with clock and input
signals, R
T
and R
B
should be low-impedance points. For cir-
cuits in which the reference is not varied, a bypass capacitor
to ground is recommended. If the reference inputs are varied
dynamically (as in an Automatic Gain Control circuit), a
low-impedance reference source is required.
RT
= 0.00V and V
RB
= -1.00V. These
A reference middle, R
as an input to adjust the mid-scale point in order to improve
integral linearity. This point may also be used as a tap to sup-
ply a mid-scale voltage to offset the analog input. If V
used as an output, it must be connected to a high input
impedance device which has small input current. Noise at
this point may adversely affect the performance of this
device.
M
, is also provided; this may be used
RM
is
Controls
Two function control pins, NMINV and NLINV, set the out-
put format to be either straight binary or offset two’s comple-
ment, in either true or inverted sense, according to Table 1.
These pins are active LOW as signified by the prefix "N" in
the signal name. They may be tied to VCC for a logic "1" and
DGND for a logic "0."
NMINV controls the MSB, D
LSBs: D
2
, D
3
and D
1
; NLINV controls the three
4
.
Convert
The TDC1044A requires a CONVert (CONV) signal. A sam-
ple is taken (the comparators are latched) within t
rising edge of CONV. The coded result is translated to the
output latches on the next rising edge. The outputs hold the
previous data a minimum time (t
the CONV signal. New data becomes valid after a maximum
delay time, t
D
.
STO
after a
HO
) after the rising edge of
Analog Input
The TDC1044A uses latching comparators which cause the
input impedance to vary slightly with the signal level. For
optimal performance, the source impedance of the driving
circuit must less than 25 Ohms. Within the range of V
+0.5V, the input signal will not damage the device. If the
input signal is at a voltage between V
will be a binary code between 0 and 15 inclusive. A signal
outside this range will indicate either full-scale positive or
full-scale negative, depending on whether the signal is off-
scale in the positive or negative direction.
EE
to
RT
and V
RB
, the output
Outputs
TDC1044A outputs are TTL compatible, and capable of
driving four low-power Schottky TTL (54/74 LS) unit loads.
The outputs hold the previous data a minimum time (t
after the rising edge of the CONV signal. Data becomes
valid after a maximum delay time (t
of CONV. For optimum performance, 2.2 kOhm pull-up
resistors are recommended.
HO
)
D
) after the rising edge
No Connects
Pin 3 of the TDC1044A is labeled No Connect (NC), and has
no connection to the chip. Connect this pin to A
noise performance.
GND
for best
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