參數(shù)資料
型號(hào)： TDA9965HL/C3,118
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 21/22頁(yè)
文件大?。?/td> 137K
代理商： TDA9965HL/C3,118
2004 Jul 05
8
Philips Semiconductors
Product specication
12-bit, 5.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9965
tW(SHD)
SHD pulse width
Vi(IN) = 1000 mV;
transition (99%) in 1 pixel;
code fco(CTH) = 0000;
see Fig.5
9
ns
code fco(CTH)
0000
8
ns
0001
13
ns
0010
17
ns
0100
23
ns
1000
33
ns
1111
51
ns
th(IN-SHP)
CTH input hold time compared
to control pulse SHP
see Fig.5
3
ns
th(IN-SHD)
CTH input hold time compared
to control pulse SHD
see Fig.5
3
ns
Programmable Gain Amplier (PGA) output: pin PGAOUT
VPGAOUT(p-p)
PGA output amplier dynamic
voltage level
(peak-to-peak value)
2000
mV
VPGAOUT(b)
PGA output amplier black
level voltage
code C(CLP) =0
1.475
V
ZPGAOUT
PGA output amplier output
impedance
fpix at 10 kHz for minimum
and maximum values
5
IPGAOUT
PGA output current drive
static
1mA
GPGA(min)
minimum gain of PGA circuit
code GPGA =0
0
dB
GPGA(max)
maximum gain of PGA circuit
code GPGA ≥767
36
dB
Analog-to-Digital Converter (ADC)
fpix(max)
maximum pixel frequency
30
MHz
tW(CLKADC)H
CLKADC pulse width HIGH
Vi(IN) = 1000 mV;
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128; see Fig.5
12
ns
tW(CLKADC)L
CLKADC pulse width LOW
Vi(IN) = 1000 mV;
transition (99.5%) in 1 pixel;
code fco(CTH) = 0000;
code GPGA = 128
12
ns
SRCLKADC
CLKADC input slew rate
rising and falling edges;
10% to 90%
0.5
V/ns
Vi(ADCIN)(p-p)
ADC input voltage
(peak-to-peak value)
with internal regulator
2
V
Ii(ADCIN)
ADC input current
2
+120
A
VRB
ADC reference voltage bottom
1.30
V
VRT
ADC reference voltage top
3.65
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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