參數(shù)資料
型號(hào): TDA9965
廠商: NXP Semiconductors N.V.
英文描述: 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras
中文描述: 12位,5.0 V固定,30 Msps的模擬到數(shù)字的CCD相機(jī)接口
文件頁(yè)數(shù): 8/22頁(yè)
文件大小: 137K
代理商: TDA9965
2004 Jul 05
8
Philips Semiconductors
Product specification
12-bit, 5.0 V, 30 Msps analog-to-digital
interface for CCD cameras
TDA9965
t
W(SHD)
SHD pulse width
V
i(IN)
= 1000 mV;
transition (99%) in 1 pixel;
code f
co(CTH)
= 0000;
see Fig.5
code f
co(CTH)
0000
0001
0010
0100
1000
1111
see Fig.5
9
ns
8
13
17
23
33
51
3
ns
ns
ns
ns
ns
ns
ns
t
h(IN-SHP)
CTH input hold time compared
to control pulse SHP
CTH input hold time compared
to control pulse SHD
t
h(IN-SHD)
see Fig.5
3
ns
Programmable Gain Amplifier (PGA) output: pin PGAOUT
V
PGAOUT(p-p)
PGA output amplifier dynamic
voltage level
(peak-to-peak value)
PGA output amplifier black
level voltage
PGA output amplifier output
impedance
PGA output current drive
minimum gain of PGA circuit
maximum gain of PGA circuit
2000
mV
V
PGAOUT(b)
code C
(CLP)
= 0
1.475
V
Z
PGAOUT
f
pix
at 10 kHz for minimum
and maximum values
static
code G
PGA
= 0
code G
PGA
767
5
I
PGAOUT
G
PGA(min)
G
PGA(max)
Analog-to-Digital Converter (ADC)
0
36
1
mA
dB
dB
f
pix(max)
t
W(CLKADC)H
maximum pixel frequency
CLKADC pulse width HIGH
30
12
MHz
ns
V
i(IN)
= 1000 mV;
transition (99.5%) in 1 pixel;
code f
co(CTH)
= 0000;
code G
PGA
= 128; see Fig.5
V
i(IN)
= 1000 mV;
transition (99.5%) in 1 pixel;
code f
co(CTH)
= 0000;
code G
PGA
= 128
rising and falling edges;
10% to 90%
with internal regulator
t
W(CLKADC)L
CLKADC pulse width LOW
12
ns
SR
CLKADC
CLKADC input slew rate
0.5
V/ns
V
i(ADCIN)(p-p)
ADC input voltage
(peak-to-peak value)
ADC input current
ADC reference voltage bottom
ADC reference voltage top
2
V
I
i(ADCIN)
V
RB
V
RT
2
1.30
3.65
+120
μ
A
V
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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