參數(shù)資料
型號(hào)： TDA9917HW/12/C1
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP48
封裝： 7 X 7 MM, 1.00 MM HEIGHT, PLASTIC, MS-026, SOT545-2, QFP-48
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 120K
代理商： TDA9917HW/12/C1
TDA9917_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 9 June 2006
7 of 20
Philips Semiconductors
TDA9917
8-bit, up to 250 Msample/s Analog-to-Digital Converter (ADC)
[1]
The circuit has two clock inputs: CLK+ and CLK
. There are 2 modes of operation:
a) LVDS mode: CLK+ and CLK
inputs are at differential LVDS levels. An external resistor between 80 and 120 is needed.
b) 1.8 V CMOS mode: CLK+ input is at 1.8 V CMOS level and sampling is taken on the rising edge of the clock input signal. In that case
pin CLK
has to be grounded.
[2]
|V
gpd| represents the ground potential difference voltage. This is the voltage that results from current owing through the nite resistance
and the inductance between the receiver and the driver circuit ground voltages.
[3]
Guaranteed by design.
[4]
The ADC input range can be adjusted with an external reference voltage supplied to pin FSREF. This voltage has to be referenced to
AGND.
10. Dynamic characteristics
Voltage controlled regulator output: pin CMADC
VO(cm)
common-mode output voltage
-
0.95
-
V
Reference voltage input: pin FSREF[4]
Vref(fs)
full-scale reference voltage
internal reference
-
0
-
V
external reference
-
1.25
-
V
Ii(FSREF)
input current on pin FSREF
-
12
-
A
Vi(p-p)(max)
maximum peak-to-peak input
voltage
<tbd>
2.0
<tbd>
V
Digital outputs: pins D0 to D7, CCS and IR
VOL
LOW-level output voltage
OGND
-
0.4
V
VOH
HIGH-level output voltage
0.85VCCO
-VCCO
V
Table 6.
Static characteristics …continued
VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
Tamb = 40 °C to +85 °C; Vi(IN) Vi(INN) = 2.0 V 0.5 dB; VI(cm) = 0.95 V; Vref(fs) = 0 V; typical values are measured at
VCCA = 3.3 V and VCCD =VCCO = 1.8 V, Tamb =25 °C and CL = 10 pF; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 7.
Dynamic characteristics
VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together;
Tamb = 40 °C to +85 °C; Vi(IN) Vi(INN) = 2.0 V 0.5 dB; VI(cm) = 0.95 V; Vref(fs) = 0 V; typical values are measured at
VCCA = 3.3 V and VCCD =VCCO = 1.8 V, Tamb =25 °C and CL = 10 pF; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock timing input: pins CLK+ and CLK
fclk(min)
minimum clock frequency
-
<tbd>
Msample/s
fclk(max)
maximum clock frequency
TDA9917HW/12
125
-
Msample/s
TDA9917HW/25
250
-
Msample/s
tw(clk)
clock pulse width
fclk = 125 Msample/s
2
-
ns
fclk = 250 Msample/s
2
-
ns
Timing output: pins D0 to D7 and IR[1] (see Figure 3)
td(s)
sampling delay time
1.8 V CMOS clock
-
1.2
<tbd>
ns
LVDS clock
-
1.7
<tbd>
ns
th(o)
output hold time
1.8 V CMOS clock
3.5
4.4
-
ns
LVDS clock
4.2
4.9
-
ns
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