參數(shù)資料
型號(hào): TDA9886HN/V3
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: AM/FM, AUDIO/VIDEO DEMODULATOR, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-3, HVQFN-32
文件頁數(shù): 7/56頁
文件大?。?/td> 248K
代理商: TDA9886HN/V3
2003 Oct 02
15
Philips Semiconductors
Product specication
I2C-bus controlled single and multistandard
alignment-free IF-PLL demodulators
TDA9885; TDA9886
9.1.1
SLAVE ADDRESS
The first module address MAD1 is the standard address (see Table 1).
Table 4
Slave addresses; notes 1 and 2
Notes
1. For MAD activation via external resistor: see Table 1 and Fig.23.
2. For applications without I2C-bus: see Tables 17 and 18.
9.1.2
DATA BYTE
Table 5
Data read register (status register)
Table 6
Description of status register bits
Note
1. If no IF input is applied, then bit AFCWIN = 1 due to the fact that the VCO is forced to the AFC window border for
fast lock-in behaviour.
SLAVE ADDRESS
BIT
NAME
VALUE (HEX)
A6
A5
A4
A3
A2
A1
A0
MAD1
43
1
0
1
MAD2
42
1
0
1
0
MAD3
4B
1
0
1
0
1
MAD4
4A
1
0
1
0
1
0
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
AFCWIN
VIFLEV
CARRDET
AFC4
AFC3
AFC2
AFC1
PONR
BIT
VALUE
DESCRIPTION
AFCWIN
AFC window
1
VCO in
±1.6 MHz AFC window; note 1
0
VCO out of
±1.6 MHz AFC window
VIFLEV
VIF input level
1
high level; VIF input voltage
≥200 V (typically)
0
low level
CARRDET
FM carrier detection
1
detection
0
no detection
AFC[4:1]
Automatic frequency control
see Table 7
PONR
Power-on reset
1
after Power-on reset or after supply breakdown
0
after a successful reading of the status register
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