參數(shù)資料
型號(hào): TDA9859
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 音頻控制
英文描述: Universal hi-fi audio processor for TV
中文描述: 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP32
封裝: 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù): 10/20頁(yè)
文件大小: 113K
代理商: TDA9859
1997 Sep 01
10
Philips Semiconductors
Preliminary specification
Universal hi-fi audio processor for TV
TDA9859
I
2
C-BUS PROTOCOL
This circuit operates as a slave receiver only. For more information about the I
2
C-bus, see “The I
2
C-bus and how to use
it” order number 9398 393 40011.
I
2
C-bus format
Note
1.
Multiple DATA-A (acknowledge) sequences may occur.
Table 1
Explanation of I
2
C-bus format
Note
1.
If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed by the device.
Table 2
I
2
C-bus transmission
Note
1.
If auto-increment of the subaddress is used, it is necessary to insert three dummy data words between the treble
control byte and the switching control bytes.
S
SLAVE ADDRESS
W
A
SUBADDRESS
A
DATA
(1)
A
(1)
P
NAME
DESCRIPTION
S
SLAVE ADDRESS
W
A
SUBADDRESS
DATA
(1)
P
START condition (SCL HIGH, SDA HIGH-to-LOW)
100 0000 (V
25
= LOW) or 100 0001 (V
25
= HIGH)
0
acknowledge (SDA = LOW); generated by the device
subaddress (byte); see Table 2
data byte; see Table 2
STOP condition (SCL = HIGH, SDA = LOW-to-HIGH)
FUNCTION
SUBADDRESS
DATA BITS
BINARY
HEX
D7
D6
D5
D4
D3
D2
D1
D0
Loudspeaker channel
Volume control common
Volume control left
Volume control right
Bass control
Treble control
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
00
01
02
03
04
0
0
0
0
0
0
0
0
0
0
V05
0
0
0
0
V04
VL4
VR4
BA4
0
V03
VL3
VR3
BA3
TR3
V02
VL2
VR2
BA2
TR2
V01
VL1
VR1
BA1
TR1
V00
VL0
VR0
BA0
TR0
Switching control byte
SCART output
(1)
Loudspeaker output
0000 1000
0000 1001
08
09
0
MU1
MU2
P1
EF1
P2
ST
I13
I23
I12
I22
I11
I21
I10
I20
EF2
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