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參數(shù)資料
| 型號： | TDA9851T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled economic BTSC stereo decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | 7.5 MM, PLASTIC, SO-24 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 145K |
| 代理商： | TDA9851T |
1997 Nov 12
8
Philips Semiconductors
Product specification
I
2
C-bus controlled economic BTSC stereo
decoder
TDA9851
Outputs OUTL and OUTR
Z
o
V
O
R
L
output impedance
DC output voltage
output load resistance
(AC-coupled)
output load capacitance
crosstalk SAP into L and R
0.45V
CC
0.5V
CC
5
80
120
0.55V
CC
V
k
C
L
α
ct
50
70
2.5
nF
dB
100% modulation;
f
mod
= 1 kHz; SAP;
mode selector switched to
stereo
VCA
I
s
nominal timing current for
nominal release rate of VCA
detector
nominal detector release rate
I
s
can be measured at pin TW
via current meter connected to
0.5V
CC
+ 1 V
nominal timing current and
external capacitor values
6.5
8
9.5
μ
A
Rel
rate
125
dB/s
Automatic volume level control
G
v
voltage gain
maximum boost; note 2
maximum attenuation; note 2
5
14
6
15
1.5
7
16
dB
dB
dB
G
step
equivalent step width between
the input stages (soft switching
system)
input voltage (RMS value)
V
iop(rms)
maximum boost; note 2
maximum attenuation; note 2
160
0.1
1.125
200
250
V
V
mV
V
o(rms)
output voltage in AVL
operation (RMS value)
DC offset voltage between
different gain steps
V
offset(DC)
voltage at pin C
AV
7.0 to 6.83 V or
6.83 to 6.61 V or
6.61 to 5.83 V or
5.83 to 3.1 V; note 3
AT1 = 0; AT2 = 0; note 4
AT1 = 1; AT2 = 0; note 4
AT1 = 0; AT2 = 1; note 4
AT1 = 1; AT2 = 1; note 4
normal mode; CCD = 0; note 5 1.6
power-
on
speed-up; CCD = 1;
note 5
20
mV
R
att
discharge resistors for attack
time constant
340
590
0.96
1.7
420
730
1.2
2.1
2.0
30
520
910
1.5
2.6
2.4
k
k
μ
A
μ
A
I
dec
charge current for decay time
Muting at power supply voltage drop for OUTR and OUTL
V
CC
supply voltage drop for mute
active
V
CAP
0.7
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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