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參數(shù)資料
| 型號(hào)： | TDA9847T-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 146K |
| 代理商： | TDA9847T-T |
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1995 May 23
13
Philips Semiconductors
Preliminary specication
TV and VTR stereo/dual sound processor
with digital identication
TDA9847
Notes to the characteristics
1. Vo = 0.5 V (RMS value); f = 1 kHz.
2. Without de-emphasis capacitors with respect to nominal gain.
3. In dual mode: A (B)-signal into B (A) channel; in stereo mode: R-signal into left channel; L-signal = 0.
4. Tuner input signal, measured with PCALH reference front end (1
2EMF, 75 , 2T/20T/white bar, 100% video) and
PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned.
5. Bandwidth of the pilot BP-filter B3dB = 1.2 kHz. Vi2 input driven with identification-modulated pilot carrier and white
noise.
6. Identification window is defined as twice the pull-in frequency range (lower plus upper side) of identification PLL
(steady detection) plus window increase due to integrator (fluctuating detection).
7. The maximal total system identification time on is equal to tident(on) plus tacqui AGC.
8. The maximal total system identification time off is equal to tident(off).
tident(on)
total identication time on
stereo; note 7
0.35
2.0
s
dual; note 7
0.35
2.0
s
tident(off)
total identication time off
stereo; note 8
0.60
1.5
s
dual; note 8
0.60
1.5
s
LED (pins 18 and 19)
VL(off)
output voltage
LED off
8.8
V
VL(on)
output voltage
LED on
0.7
V
IL(off)
input current
LED off
1
A
IL(on)
input current
LED on
12
mA
Control input ports C1 to C3 (pins 1, 2 and 24)
VIL
LOW level input voltage
0
0.8
V
VIH
HIGH level input voltage
2.0
5.0
8.8
V
IIL
LOW level input current
-1
A
IIH
HIGH level input current
1
A
Control input Port C4 (pin 3)
VIL
LOW level input voltage
0
0.8
V
VCT
3-state level input voltage
1.5
1.8
2.1
V
VIH
HIGH level input voltage
2.8
5.0
8.8
V
IIL
LOW level input current
1
A
ICT
3-state level input current
1
A
IIH
HIGH level input current
1
A
th1
HIGH level hold time
see Fig.5
5
s
th2
LOW level hold time
see Fig.5
5
s
tsu1
HIGH level set-up time
see Fig.5
0.25
s
tsu2
LOW level set-up time
see Fig.5
0.25
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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