參數(shù)資料
型號： TDA9330H
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： I2C-bus controlled TV display processors
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, QFP-44
文件頁數(shù)： 25/56頁
文件大?。?/td> 228K
代理商： TDA9330H
2000 May 08
25
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV display processors
TDA933xH series
t
jitter (
σ
)
1f
H
mode; note 36
2f
H
mode; note 36
1.4
1.0
ns
ns
S
ANDCASTLE OUTPUT
;
PIN
9; note 37
V
SCO(0)
I
sink
V
o(SCO)
zero level
sink current
output voltage
0
0.5
4.2
2.3
0.5
1.0
0.5
0.7
4.5
2.5
0.7
1.0
0.9
4.8
2.7
0.9
3.5
V
mA
V
V
mA
mA
during clamp pulse
during blanking
I
source
I
i(grd)
source current
guard pulse input current required
to stop the blanking after a vertical
blanking period
pulse width in 1f
H
mode
note 38
t
W(1)
clamp pulse, 22 LLC
pulses
vertical blanking (50/60 Hz)
clamp pulse, 22 LLC
pulses
clamp pulse, HDTV = 1,
HDCL = 1, 18 LLC; see
Fig.11
vertical blanking;
depends onVWAITsetting;
see Fig.13
1f
H
mode, 37 LLC pulses
2f
H
mode, 37 LLC pulses
2f
H
mode, HDCL = 1,
14 LLC pulses, see Fig.11
3.2
μ
s
22/17
1.6
lines
μ
s
t
W(2)
pulse width in 2f
H
mode
1.22
μ
s
t
d(bk-HD)
delay between start H
D
pulse and
start of clamp pulse
5.4
2.7
0.94
μ
s
μ
s
μ
s
Vertical synchronization and geometry processing
V
D
INPUT SIGNAL
;
PIN
23
V
IL
V
IH
I
i(VD)
t
r(VD)
t
f(VD)
t
W(VD)
V
ERTICAL DIVIDER AND RAMP GENERATOR
;
PINS
15
AND
16; note 39
LOW-level of input voltage
HIGH-level of input voltage
input current
rise time
fall time
pulse width
2.0
10
0.5
0.8
5.5
+10
100
100
63.5
V
V
μ
A
ns
ns
lines
N
h
number of lines per field
(VGA mode is valid only for
TDA9331H and TDA9332H)
1f
H
TV mode
1f
H
VGA mode
2f
H
; 2f
V
; TV mode
2f
H
; 1f
V
; TV mode
2f
H
VGA mode
244
175
244
488
350
511.5
450
511.5
1023.5
900
lines
lines
lines
lines
lines
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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