參數(shù)資料
型號(hào)： TDA9109/S
廠商： STMICROELECTRONICS
元件分類(lèi)： 偏轉(zhuǎn)
英文描述： HORIZ/VERT DEFLECTION IC, PDIP32
封裝： SHRINK, PLASTIC, DIP-32
文件頁(yè)數(shù)： 10/30頁(yè)
文件大?。?/td> 293K
代理商： TDA9109/S
6
7
PLL1F
(Loop Filter)
R0
1.6V
6.4V
5
C0
6.4V
1.6V
0 0.875T
H TH
RS
FLIP FLOP
(1.3V < V
< 6V)
7
I0
2
4 I0
I
0
(0.80 < a < 1.30)
a
I2C Free Running
Adjustment
91
09
S
-2
9.
E
P
S
Figure 9 : Details of VCO
LOCKDET
COMP1
INPUT
INTERFACE
H/HVIN
High
CHARGE
PUMP
Low
PLL
INHIBITION
VCO
7
6
5
PLL1F
R0
C0
PHASE
ADJUST
E2
I2C
HPOS
Adj.
OSC
Tramext
I2C
Forced
Frequency
Lock/Unlock
Status
8
HPOSITION
1
91
09
S
-2
8
.E
P
S
Figure 8 : Block Diagram
OPERATING DESCRIPTION (continued)
7
PLL1F
1
m F
4.7
m F
1.8k
W
91
09
S
-2
7
.E
P
S
Figure 7
II.2 - PLL1
The PLL1 consists of a phase comparator, an exter-
nal filter and a voltage-controlled oscillator (VCO).
The phase comparator is a "phase frequency" type
designed in CMOS technology. This kind of phase
detector avoids locking on wrong frequencies. It is
followed by a "charge pump", composed of two
current sources : sunk and sourced (typically I = 1mA
when locked and I = 140
A when unlocked). This
difference between lock/unlock allows smooth catch-
ing of the horizontal frequency by PLL1. This effect
is reinforced by an internal original slow down system
when PLL1 is locked, avoiding the horizontal fre-
quency changing too quickly.
The dynamic behaviour of PLL1 is fixed by an exter-
nal filter which integrates the current of the charge
pump. A "CRC" filter is generally used (see Figure 7).
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase compara-
tor.The inhibition is done by a switch located be-
tween the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current propor-
tional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6V and 6.4V.
The control voltage of the VCO is between 1.33V
and 6V (see Figure 9). The theorical frequency
range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on the filter lowest
value. To remove the device and external compo-
nents spread, it is possible to adjust the free run-
ning frequency through I
2C. This adjustment can
be done automatically on the manufacturing line
without manual operation by using Hlock/unlock
information. The adjustment range is 0.8 to 1.3 f0
(where 1.3 f0 is the free running frequency at power
on reset).
TDA9109/S
18/30
相關(guān)PDF資料
PDF描述
TDA9111 HORIZ/VERT DEFLECTION IC, PDIP32
TDA9112A HORIZ/VERT DEFLECTION IC, PDIP32
TDA9112 HORIZ/VERT DEFLECTION IC, PDIP32
TDA9113 HORIZ/VERT DEFLECTION IC, PDIP32
TDA9115 HORIZ/VERT DEFLECTION IC, PDIP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TDA9109SN 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
TDA9110 制造商:STMicroelectronics 功能描述:TDA9110 - Bulk
TDA9111 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
TDA9112 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
TDA9112A 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:HIGH-END I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*