
1996 Jun 04
7
Philips Semiconductors
Product specification
10-bit, 1000 Msps Digital-to-Analog
Converter (DAC)
TDA8776A
Notes
1.
2.
D0 to D9 connected to either HIGH or LOW level, CLK is HIGH and CLK is LOW.
The analog output voltages (V
OUT
and V
OUT
) are negative with respect to AGND (see Table 1). The external output
resistance between AGND and each of these outputs is typically 50
.
Due to on-chip regulator behaviour a warm-up time is necessary to reach optimal performances; a typical time is
1 minute.
Devices with higher SFDR (min.) can be delivered on special request.
The worst case characteristics are obtained at the transition from input code 0 to 1023 and if an external load
impedance greater than 50
is connected between V
OUT
or V
OUT
and AGND in parallel with the external 50
load.
The specified values have been measured directly on a 50
load between V
OUT
and AGND. No further load
impedance between V
OUT
and AGND has been applied. All input data is latched at the falling edge of the clock.
The data set-up (t
SU;DAT
) is the minimum period preceding the falling edge of the clock that the input data must be
stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
falling edge of the clock and still be recognized. The data hold time (t
HD;DAT
) is the minimum period following the
falling edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time
indicates that the data may be released prior to the falling edge of the clock and still be recognized.
The definition of glitch energy and the measurement set-up are shown in Fig.10. The glitch energy is measured at
the input transition between code 511 to 512.
3.
4.
5.
6.
7.
Table 1
Input coding and DAC output voltages (typical values; referenced to AGND regardless of the offset voltage)
Switching characteristics (f
clk
= 1000 MHz);
notes 5 and 6; see Figs 8 and 9
t
SU;DAT
t
HD;DAT
t
PD
t
S1
t
S2
t
d
data set-up time
data hold time
propagation delay time
settling time
settling time
input to 50% output delay time
100
400
150
0.8
0.5
2.0
1.4
500
0.9
1.5
ps
ps
ns
ns
ns
ns
10% to 90% full scale
change to
±
1 LSB
Output transients; glitches (f
clk
= 1000 MHz);
note 7; see Fig.10
E
g
differential glitch energy from code
transition 511 to 512
1
2
pV.s
CODE
BINARY INPUT DATA
DAC OUTPUT
VOLTAGES (V)
Z
L
= 50
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V
OUT
0
0.0010
.
0.5
.
0.9990
1.0
V
OUT
1.0
0.9990
.
0.5
.
0.0010
0
0
1
.
0
0
.
1
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
0
.
0
.
1
1
0
1
.
0
.
0
1
512
.
1022
1023
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT