參數(shù)資料
型號(hào): TDA8768AH5
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: 12-bit, 70 Msps Analog-to-Digital Converter (ADC)
中文描述: 12位,70 Msps的模擬到數(shù)字轉(zhuǎn)換器(ADC)
文件頁(yè)數(shù): 12/32頁(yè)
文件大?。?/td> 915K
代理商: TDA8768AH5
Philips Semiconductors
TDA8768A
12-bit, 70 Msps Analog-to-Digital Converter (ADC)
Product data
Rev. 02 — 03 July 2002
12 of 32
9397 750 09656
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
[1]
Twos complement reference is inverted MSB.
[1]
X = don’t care.
Table 7:
Output coding with differential inputs (typical values to AGND);
V
i(p-p)
V
i(p-p)
= 1.9 V, V
ref
= V
CCA3
1.75 V
V
i(p-p)
V
i(p-p)
IR
Binary outputs
Code
Twos complement
outputs
[1]
D11 to D0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 00
1 0 0 0 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1
D11 to D0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
Underflow
0
1
2047
4094
4095
Overflow
<3.125
3.125
3.6
4.075
>4.075
>4.075
4.075
3.6
3.125
<3.125
0
1
1
1
1
1
0
Table 8:
OTC
0
1
X
[1]
Mode selection
CE
0
0
1
D0 to D11 and IR
binary; active
twos complement; active
high-impedance
Table 9:
SH
1
0
Sample-and-hold selection
Sample-and-hold
active
inactive; tracking mode
Fig 3.
Timing diagram.
ds
t
sample N + 1
sample N
CLK
MBG855
sample N + 2
V
DATA
D0 to D11
td
th
tCLKL
tCLKH
HIGH
LOW
50 %
HIGH
LOW
50 %
DATA
N
+
1
DATA
N
DATA
N
1
DATA
N
2
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