參數(shù)資料
型號: TDA8766G
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter
中文描述: 1-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP32
封裝: 5 X 5 X 1.40 MM, PLASTIC, LQFP-32
文件頁數(shù): 8/20頁
文件大?。?/td> 175K
代理商: TDA8766G
1996 Mar 20
8
Philips Semiconductors
Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
Analog input voltages producing code 0 up to and including 1023:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
°
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to 1023 at T
amb
= 25
°
C.
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins V
RB
and V
RT
via offset resistors R
OB
and R
OT
as shown in Fig.3.
2.
3.
a) The current flowing into the resistor ladder is I
L
=
and the full-scale input range at the converter,
to cover code 0 to code 1023, is
b) Since R
L
, R
OB
and R
OT
have similar behaviour with respect to process and temperature variation, the ratio
R
R
OB
R
L
R
OT
+
+
will be kept reasonably constant from part to part. Consequently variation of the output codes
at a given input voltage depends mainly on the difference V
RT
V
RB
and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
E
FFECTIVE BITS
; see Fig.9; note 5
EB
effective bits
f
clk
= 20 MHz
f
i
= 300 kHz
f
i
= 1 MHz
f
i
= 3.58 MHz
9.5
9.3
8.0
bits
bits
bits
Timing (f
clk
= 20 MHz; C
L
= 20 pF);
see Fig.4; note 6
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
5
8
8
8
12
17
21
5
15
20
24
ns
ns
ns
ns
ns
V
DDO
= 4.75 V
V
DDO
= 3.15 V
V
DDO
= 2.7 V
3-state output delay times;
see Fig.5
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
14
16
16
14
18
20
20
18
ns
ns
ns
ns
Standby mode output delay times
t
dSTBLH
t
dSTBHL
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
200
500
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
V
+
R
OB
R
L
R
L
R
OT
+
-----------------------------------------
V
I
R
L
I
L
×
OB
R
OT
+
+
R
V
RT
V
RB
(
)
0.871
V
RT
V
RB
(
)
×
=
×
=
=
-----------------------------------------
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