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參數(shù)資料
| 型號： | TDA8765 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 10-bit high-speed Analog-to-Digital Converter ADC |
| 中文描述： | 10位高速模擬數(shù)字轉(zhuǎn)換器模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 156K |
| 代理商： | TDA8765 |
1999 Jan 06
10
Philips Semiconductors
Preliminary specification
10-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8765
Notes
1.
The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1 (DC level varies equal to DC level of V
CCD
): CLK and CLK inputs are at differential PECL levels.
b) PECL mode 2 (DC level varies equal to DC level of V
CCD
): CLK input is at PECL level and sampling is taken on
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
c) PECL mode 3 (DC level varies equal to DC level of V
CCD
): CLK input is at PECL level and sampling is taken on
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with
a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
It is possible with an external reference connected to pin V
ref
to adjust the ADC input range. This voltage has to be
referenced to V
CCA
. For V
CCA
1.825 V, the differential input voltage amplitude is 2 V (p-p).
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.
2.
3.
4.
THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
(2nd)2
+
+
+
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N
bit
×
6.02 + 1.76 dB.
Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (
6 dB
below full scale for each input signal).
d
3
is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation
product.
Output data acquisition: the output data is available after the maximum delay of t
d
.
5.
6.
7.
Timing (C
L
= 10 pF);
see Fig.5 and note 7
t
d(s)
t
h
t
d
sampling delay time
output hold time
output delay time
4
10
13
2
15
18
ns
ns
ns
ns
V
CCO
= 5.25 V
V
CCO
= 3.0 V
3-state output delay times;
see Fig.6
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
14
16
16
14
18
20
20
18
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
THD
20 log
(3rd)2
(4th)2
(5th)2
(6th)2
+
-----------------------------------------------------F
=
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| TDA8766 | 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TDA8765H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed Analog-to-Digital Converter ADC |
| TDA8765H/4 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed Analog-to-Digital Converter ADC |
| TDA8765H/5 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed Analog-to-Digital Converter ADC |
| TDA8766 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed 2.7 to 5.25 V analog-to-digital converter |
| TDA8766G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed 2.7 to 5.25 V analog-to-digital converter |
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