參數(shù)資料
型號(hào): TDA8764TS
廠商: NXP Semiconductors N.V.
英文描述: 10-bit high-speed low-power ADC with internal reference regulator
中文描述: 10位高速低的內(nèi)部參考調(diào)節(jié)功率ADC
文件頁(yè)數(shù): 12/28頁(yè)
文件大?。?/td> 184K
代理商: TDA8764TS
1999 Jan 12
12
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
T
WO
-
TONE
; note 9
TTID
two-tone intermodulation distortion
f
clk
= 40 MHz
f
clk
= 80 MHz
tbf
tbf
dB
dB
B
IT ERROR RATE
BER
bit error rate
f
i
= 5 MHz; V
i
=
±
16 LSB at
code 512
f
clk
= 40 MHz
10
13
times/
sample
times/
sample
f
clk
= 80 MHz
10
13
Timing (f
clk
= 40 MHz; C
L
= 10 pF) /4 version;
see Fig.5 and note 10
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
5
tbf
tbf
12
11
2
tbf
tbf
10
tbf
ns
ns
ns
ns
pF
V/
μ
s
V
CCO
= 2.7 V
V
CCO
= 3.3 V
C
L
SR
digital output load capacitance
slew rate
V
CCO
= 2.7 V; C
L
= 10 pF
Timing (f
clk
= 80 MHz; C
L
= 10 pF) /8 version;
see Fig.5 and note 10
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
4
tbf
tbf
8
7
2
tbf
tbf
10
tbf
ns
ns
ns
ns
pF
V/
μ
s
V
CCO
= 2.7 V
V
CCO
= 3.3 V
C
L
SR
digital output load capacitance
slew rate
V
CCO
= 2.7 V; C
L
= 10 pF
3-state output delay times (f
clk
= 40 MHz) /4 version;
see Fig.6
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
3-state output delay times (f
clk
= 80 MHz) /8 version;
see Fig.6
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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