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參數(shù)資料
| 型號： | TDA8762M |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 10-bit high-speed low-power analog-to-digital converter |
| 中文描述： | 10位高速低功耗模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 162K |
| 代理商： | TDA8762M |
1996 Mar 28
9
Philips Semiconductors
Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
Analog input voltages producing code 0 up to and including code 1023:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
°
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to code 1023 at T
amb
= 25
°
C.
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins V
RB
and V
RT
via offset resistors R
OB
and R
OT
as shown in Fig.3.
2.
3.
a) The current flowing into the resistor ladder is I
L
=
and the full-scale input range at the converter,
to cover code 0 to code 1023, is .
.
b) Since R
L
, R
OB
and R
OT
have similar behaviour with respect to process and temperature variation, the ratio
R
R
OB
R
L
R
OT
+
+
will be kept reasonably constant from part to part. Consequently variation of the output codes
at a given input voltage depends mainly on the difference V
RT
V
RB
and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
4.
.
D
IFFERENTIAL GAIN
; note 9
G
diff
differential gain
f
clk
= 40 MHz;
PAL modulated ramp
0.5
%
D
IFFERENTIAL PHASE
; note 9
diff
differential phase
f
clk
= 40 MHz;
PAL modulated ramp
0.5
deg
Timing (f
clk
= 40 MHz; C
L
= 15 pF);
see Fig.4; note 10
t
ds
t
h
t
d
C
L
sampling delay time
output hold time
output delay time
digital output load
5
10
15
2
14
40
ns
ns
ns
pF
3-state output delay times;
see Fig.5
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
45
25
12
12
50
35
15
15
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
V
–
OB
R
L
R
R
L
R
OT
+
R
V
I
R
L
I
L
×
R
OB
R
OT
+
+
-----------------------------------------
V
RT
V
RB
–
(
)
0.824
V
RT
V
RB
–
(
)
×
=
×
=
=
-----------------------------------------
GER
V
----------------------------------------2 V
V
–
2 V
100
×
=
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TDA8762M/2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| TDA8762M/4 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power analog-to-digital converter |
| TDA8763 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power ADC with internal reference regulator |
| TDA8763A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power ADC |
| TDA8763AM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power ADC |
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