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參數(shù)資料
| 型號： | TDA8761A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 9-bit analog-to-digital converter for digital video |
| 中文描述： | 9位模擬數(shù)字轉(zhuǎn)換器的數(shù)字視頻 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 166K |
| 代理商： | TDA8761A |
1998 Nov 03
9
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
Analog input voltages producing code 0 up to and including code 511:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
°
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at T
amb
= 25
°
C.
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins V
RB
and V
RT
via offset resistors R
OB
and R
OT
as shown in Fig.3.
2.
3.
a) The current flowing into the resistor ladder is
and the full-scale input range at the converter,
to cover code 0 to code 511, is
b) Since R
L
, R
OB
and R
OT
have similar behaviour with respect to process and temperature variation, the ratio
R
R
OB
R
L
R
OT
+
+
will be kept reasonably constant from device to device. Consequently variation of the output
codes at a given input voltage depends mainly on the difference V
RT
V
RB
and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
f
i
= 10 MHz and f
clk
= 30 MHz; f
i
= 8 MHz and f
clk
= 20 MHz.
(
)
V
–
i(p-p)
4.
5.
6.
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
7.
Timing (f
clk
= 30 MHz; C
L
= 15 pF)
; see Fig.4; note 11
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
4
3
10
12
13
15
15
ns
ns
ns
ns
pF
V
CCO
= 4.75 V
V
CCO
= 3.15 V
C
L
digital output load
3-state output delay times
; see Fig.5
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
5.5
12
19
12
8.5
15
24
15
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
L
V
V
+
R
OB
R
L
R
OT
+
-----------------------------------------
=
V
I
R
L
I
L
×
R
R
L
R
OB
R
OT
+
+
-----------------------------------------
=
=
V
RT
(
×
V
RB
)
–
0.852
V
(
RT
V
RB
)
–
×
=
-----------------------------------------
GER
V
-----------------V
V
0
–
100
×
=
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TDA8761AM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-bit analog-to-digital converter for digital video |
| TDA8761M | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:9-bit analog-to-digital converter for digital video |
| TDA8762 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power analog-to-digital converter |
| TDA8762A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power analog-to-digital converter |
| TDA8762AM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:10-bit high-speed low-power analog-to-digital converter |
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