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參數(shù)資料
| 型號： | TDA8730 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | PLL FM demodulator for DBS signals |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 62K |
| 代理商： | TDA8730 |
March 1991
7
Philips Semiconductors
Preliminary specification
PLL FM demodulator for DBS signals
TDA8730
Notes
1.
The supply current is the consumption of the circuit only.
The current consumption of this application is given by the addition of the supply current of the circuit plus the current
consumption of external components in the application given. In this event (Fig.4) the typical current is 80 mA.
The circuit of Fig.4 is designed for an input level of 70 dB
μ
V.
The maximum allowable input level for PLL design is 74 dB
μ
V.
However, for levels other than 70 dB
μ
V the optimum loop filter values will be different from those given in Fig.4.
In the application circuit of Fig.4 the RF input is asymmetrically driven.
In order to reduce the influence of oscillator signal coupling to the RF inputs, it is recommended to use a symmetrical
drive at both inputs.
The linearity is specified as the maximum difference between the slope df/dV at the channel centre frequency
(480 MHz) and the slope at 480 MHz
±
10 MHz.
Measurements with test signals in accordance with CCIR Rec. 473-3; Fm signal with DBS parameters: pre-and
de-emphasis in accordance with CCIR Rec. 405-1, 625 lines PAL TV system. Modulator sensitive 13.5 MHz/V at
pre-emphasis cross over frequency 1 V(p-p) video signal at pre-emphasis filter input.
For the intermodulation measurement, an FM test signal is applied having the following modulating components:
1.5 MHz reference sinewave with a deviation of 9.45 MHz(p-p), 5.5 and 5.75 MHz sinewaves with deviation
5.6 MHz(p-p) (so 4.5 dB below the reference, see Fig.3). At the demodulator output the 2nd order intermodulation is
defined according to Fig.3. The video output is loaded with 500
resistor + DC blocking capacitor.
The voltage applied at pin 16 is allowed to be higher than the minimum supply voltage (8.1 V).
The voltage at the AGC output (pin 1) decreases when the RF input level at pin 13 increases above the adjusted
AGC threshold.
The DC level at the video output decreases when the RF input frequency increases.
The DC level at the video output (pin 9) is measured with the VCO switched off because when the oscillator is
operating, the DC level is dependent on the application (oscillator into the input).
10. The load impedance must have at least the minimum value for a frequency range from DC to the bandwidth of the
i.f. filter (usually 27 MHz) since wide-band noise components will also appear at the video output.
11. It is possible to use the regulator output voltage (pin 11). The maximum current allowed is 1 mA.
Possible application as voltage reference source for AFC circuit.
2.
3.
4.
5.
6.
7.
8.
9.
Video output
V
O
video output signal amplitude
(
f = 13.5 MHz p-p)
DC level of video output
pin 9 to pin 10 or pin 15
1.1
V
V
O(DC)
pin 9 to pin 10 or pin 15;
note 9
pin 9
pin 9; note 10
3.1
3.5
3.9
V
Z
O
Z
L
output impedance
AC load impedance
600
30
50
Voltage regulator
V
ref
V
reg
I
load
reference voltage for
I
load
≤
1 mA
line regulation 8.1 V
≤
VIN
≤
9.9 V
allowable load current
pin 11; note 11
pin 11
pin 11
1
7
70
0
V
mV
mA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX
.
UNIT
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