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參數(shù)資料
| 型號(hào)： | TDA8706T |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | ADC |
| 英文描述： | 6-bit analog-to-digital converter with multiplexer and clamp |
| 中文描述： | 3-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | TDA8706T |
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1996 Aug 20
7
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter with
multiplexer and clamp
TDA8706
Outputs
D
IGITAL VOLTAGE OUTPUTS
(
PINS
15
TO
20) (see Table 2)
V
OL
V
OH
I
OZ
LOW level input voltage
HIGH level output voltage
output current in 3-state mode
I
O
= 1 mA
I
O
= 0.5 mA
0.4 V < V
O
< V
CCD
0
2.7
20
0.4
V
CCD
+20
V
V
μ
A
Switching characteristics
C
LOCK TIMING
(see Fig.3)
f
CLK
f
mux
t
CLK
maximum clock frequency
maximum multiplexing frequency
period
duty cycle
LOW time
HIGH time
rise time
fall time
20
10
50
45
16
22.5
4
4
50
6
6
66.6
MHz
MHZ
ns
%
ns
ns
ns
ns
CLK = V
IH
at 50%
at 50%
at 10 to 90%
at 90 to 10%
t
LOW
t
HIGH
t
CLR
t
CLF
Select signals, Clamp, Data
(see Figs 4 and 5)
t
S
t
r
t
f
t
CLPS
t
CLPH
t
CLPP
t
d
t
DH
set-up time select A, B and C
rise time A, B and band C
fall time A, B and band C
set-up time clamp asynchronous
hold time clamp asynchronous
clamp pulse
data output delay time
data hold time
35
4
4
0
0
12
6
6
3
15
24
ns
ns
ns
at 10 to 90%
at 90 to 10%
C
CLP
= 10 nF
μ
s
ns
ns
Transfer function
ILE
DLE
AILE
EB
DC integral linearity error
DC differential linearity error
AC integral linearity error
effective bits
5.7
±
0.75
±
0.5
±
2
LSB
LSB
LSB
bits
note 3
note 3
Timing
D
IGITAL OUTPUTS
T
dt
T
sto
3-state delay time
sampling time offset
see Fig.6
16
2
25
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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| TDA8708AT | 制造商:Panasonic Industrial Company 功能描述:IC |
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