參數(shù)資料
型號: TDA8706AM
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 6-bit analog-to-digital converter with multiplexer and clamp
中文描述: 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24
封裝: 5.3 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24
文件頁數(shù): 8/20頁
文件大?。?/td> 136K
代理商: TDA8706AM
1996 Jul 30
8
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
Notes
1.
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
×
6.02 + 1.76 dB.
Output data acquisition: the output data is available after the maximum delay time of t
d
.
2.
3.
Timing (f
clk
= 40 MHz; C
L
= 20 pF); T
amb
= 25
°
C; see Fig.3
O
UTPUT DATA
; note 3
t
ds
t
h
t
d
sampling delay time
output hold time
output delay time
5
12
17
18
7
15
20
21
ns
ns
ns
ns
ns
V
DDO
= 4.75 V
V
DDO
= 3.15 V
V
DDO
= 2.70 V
S
ELECT INPUT SIGNALS
SR, SG, SB
AND
CLP
t
su
set-up time SR, SG and SB
with no overlap; see Fig.3
with overlap
10% to 90%
90% to 10%
see Fig.4
10
ns
ns
ns
ns
ns
see Fig.4
t
r
t
f
t
over
rise time SR, SG and SB
fall time SR, SG and SB
R, G and B (active) overlap
time with respect to select
signals SR, SG and SB
clamp pulse time
multiplexer hold time
SR, SG and SB
4
4
0
6
6
t
CLPP
t
MH
C
CLP
= 10 nF
9
3
μ
s
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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TDA8706T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:6-bit analog-to-digital converter with multiplexer and clamp