參數(shù)資料
型號(hào): TDA8702
廠商: NXP SEMICONDUCTORS
元件分類(lèi): DAC
英文描述: 8-bit video digital-to-analog converter
中文描述: PARALLEL, 8 BITS INPUT LOADING, 0.0065 us SETTLING TIME, 8-BIT DAC, PDIP16
封裝: PLASTIC, SOT-38, DIP-16
文件頁(yè)數(shù): 2/19頁(yè)
文件大?。?/td> 120K
代理商: TDA8702
1996 Aug 23
2
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
FEATURES
8-bit resolution
Conversion rate up to 30 MHz
TTL input levels
Internal reference voltage generator
Two complementary analog voltage outputs
No deglitching circuit required
Internal input register
Low power dissipation
Internal 75
output load (connected to the analog
supply)
Very few external components required.
APPLICATIONS
High-speed digital-to-analog conversion
Digital TV including:
– field progressive scan
– line progressive scan
Subscriber TV decoders
Satellite TV decoders
Digital VCRs.
GENERAL DESCRIPTION
The TDA8702 is an 8-bit Digital-to-Analog Converter
(DAC) for video and other applications. It converts the
digital input signal into an analog voltage output at a
maximum conversion rate of 30 MHz. No external
reference voltage is required and all digital inputs are TTL
compatible.
QUICK REFERENCE DATA
Note
1.
2.
D0 to D7 connected to V
CCD
and CLK connected to DGND.
The analog output voltages (V
OUT
and V
OUT
) are negative with respect to V
CCA
(see Table 1). The output resistance
between V
CCA
and each of these outputs is typically 75
.
The
3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).
3.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
V
CCD
I
CCA
I
CCD
V
OUT
V
OUT
analog supply voltage
digital supply voltage
analog supply current
digital supply current
full-scale analog output voltage
(peak-to-peak value)
4.5
4.5
5.0
5.0
26
23
5.5
5.5
32
30
V
V
mA
mA
note 1
note 1
note 2
Z
L
= 10 k
Z
L
= 75 k
1.45
0.72
1.60
0.80
150
250
1.75
0.88
±
1/2
±
1/2
30
340
V
V
LSB
LSB
MHz
MHz
mW
ILE
DLE
f
CLK
B
P
tot
DC integral linearity error
DC differential linearity error
maximum conversion rate
3 dB analog bandwidth
total power dissipation
f
CLK
= 30 MHz; note 3
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