參數(shù)資料
型號: TDA8351
廠商: NXP SEMICONDUCTORS
元件分類: 偏轉(zhuǎn)
英文描述: DC-coupled vertical deflection circuit
中文描述: VERTICAL DEFLECTION IC, PSIP9
封裝: POWER, PLASTIC, SOT-131-2, SIP-9
文件頁數(shù): 7/16頁
文件大?。?/td> 81K
代理商: TDA8351
1999 Sep 27
7
Philips Semiconductors
Product specification
DC-coupled vertical deflection circuit
TDA8351
Notes
1.
A flyback supply voltage of
>
50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22
resistor
(dependent on I
O
and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of V
FB
has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of
33
(see application circuit Fig.6).
The linearity error is measured without S-correction and based on the same measurement principle as performed on
the screen. The measuring method is as follows:
Divide the output signal I
4
I
7
(V
RM
) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two
succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus
part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not
adjacent blocks (LENAB) are given below:
a
a
1
+
)
a
avg
a
avg
2.
;
3.
4.
Referenced to V
P
.
The V values within formulae relate to voltages at or across relative pin numbers, i.e. V
7-4
/V
1-2
= voltage value across
pins 7 and 4 divided by voltage value across pins 1 and 2.
V
9-4
AC short-circuited.
Frequency response V
7-4
/V
9-4
is equal to frequency response V
7-4
/V
1-2
.
At V
(ripple)
= 500 mV eff; measured across R
M
; f
i
= 50 Hz.
5.
6.
7.
Guard circuit
I
O
output current
not active;
V
O(guard)
= 0 V
active; V
O(guard)
= 3.6 V
I
O
= 100
μ
A
maximum leakage
current = 10
μ
A;
50
μ
A
1
4.6
2.5
5.5
40
mA
V
V
V
O(guard)
output voltage on pin 8
allowable voltage on pin 8
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LEAB
---------------------------
=
LENAB
max
a
a
min
=
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