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參數(shù)資料
| 型號(hào)： | TDA8020HL/C2 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-358-1, LQFP-32 |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | TDA8020HL/C2 |
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2003 Nov 06
20
Philips Semiconductors
Product specication
Dual IC card interface
TDA8020HL
Clock inputs (pins CLKIN1 and CLKIN2)
fext
external frequency applied
on CLKIN1 and CLKIN2
0
25
MHz
VIL
LOW-level input voltage
VDDI >2V
0
0.3VDDI
V
1.5V<VDDI <2V
0
0.15VDDI
V
VIH
HIGH-level input voltage
VDDI > 2 V
0.7VDDI
VDDI + 0.3 V
1.5V<VDDI < 2 V
0.85VDDI
VDDI + 0.3 V
ti(r), ti(f)
input transition times
0.1/fCLKIN
ns
Logic inputs (pins SAD0 and SAD1)
VIL
LOW-level input voltage
0.3
+0.3VDDI
V
VIH
HIGH-level input voltage
0.7VDDI
VDDI + 0.3 V
ILIL
LOW-level input leakage
current
±20
A
ILIH
HIGH-level input leakage
current
±20
A
Ci
input capacitance
10
pF
Interrupt line (pin IRQ ; open-drain; active LOW output)
VOL
LOW-level output voltage
Io =2mA
0.3
V
ILH
HIGH-level leakage current
10
A
Serial data input/output (pin SDA; open-drain)
VIL
LOW-level input voltage
0.3
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
6.5
V
ILH
HIGH-level leakage current
1
A
IIL
LOW-level input current
depends on the pull-up resistance
VOL
LOW-level output voltage
IOL =3mA
0.3
V
Serial clock input (pin SCL; open-drain)
VIL
LOW-level input voltage
0.3
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
6.5
V
ILH
HIGH-level leakage current
1
A
IIL
LOW-level input current
depends on the pull-up resistance
I2C-bus timings; see Figures 6 and 7
fSCL
clock frequency
0
400
kHz
tBUF
bus free time between a
STOP and START condition
1.3
s
tHD;STA
START condition hold time
after which rst clock pulse
is generated
0.6
s
tLOW
SCL LOW time
1.3
s
tHIGH
SCL HIGH time
0.6
s
tSU;STA
set-up time START condition repeated start
0.6
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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