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參數(shù)資料
| 型號(hào)： | TDA7705TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 接收器 |
| 英文描述： | AUDIO/VIDEO DEMODULATOR, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件頁(yè)數(shù)： | 5/42頁(yè) |
| 文件大?。?/td> | 396K |
| 代理商： | TDA7705TR |
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TDA7705
Function description
Doc ID 15938 Rev 8
If I2C serial bus is chosen as means of communication with the controlling device, two chip
addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins
35 and 39.
The status of pins 35 and 39 during the reset phase can be set to:
high, through external <10 k
Ω resistors tied to 3.3V (pin 32), or
low, by not forcing any voltage on them from outside, as 50 kohm internal pull-down
resistors are present on said pins.
To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and then for an
2.13.2
I2C bus protocol
I2C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires
an acknowledge after any 8-bit transmission.
A "write" communication example is shown in the figure below, for an unspecified number of
data bytes (see the relevant technical documentation for frame structure description):
Figure 3.
I2C "write" sequence
Table 3.
Boot mode pin configuration
Configuration:
I2C (addr. 0 x C2)
I2C (addr. 0 x C8)
SPI
Pin
at reset
operation
at reset
operation
at reset
operation
39
RDSINT
0
in
RDS interrupt
out
0
in
RDS interrupt
out
1
in
RDS interrupt
out
37
SCL
x
I2C SCL
in
x
I2C SCL
in
x
SPI CLK
in
36
SDA
x
I2C SDA
in/out
x
I2C SDA
in/out
x
SPI MOSI
in
35
(SPI_MISO)
0
in
-
1
in
-
1
in
SPI MISO
out
34
(SPI_CS)
x
-
x
-
x
SPI SS
in
ACK
data
STOP
clk1
clk2
…
clk8
clk9
clk1
clk2
START
ACK
d7
d6
address
a0
…
d0
…
clk8
clk9
a7
a6
…
SCL
SDA
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| TDA7705 | AUDIO/VIDEO DEMODULATOR, PQFP64 |
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