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參數(shù)資料
| 型號： | TDA758013TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件頁數(shù)： | 4/39頁 |
| 文件大?。?/td> | 616K |
| 代理商： | TDA758013TR |
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Obsolete
Product(s)
- Obsolete
Product(s)
Block diagram and electrical specifications
TDA7580
37
GPIO_SDO1
B
DSP0 GPIO for boot selection or audio
SAI0 output.
5V tolerant. DSP0
GPIO3. With internal
pull-up, on at reset [PP]
Input
38
TST4_SDI0
B
Audio SAI0 data input or test selection pin
in test mode
5V tolerant. DSP0
GPIO5. With internal
pull-up, on at reset [PP]
Input
39
TST1_SDI1
B
DSP0 GPIO for boot selection or audio
SAI1 input. Test selection pin in test
mode.
5V tolerant. DSP0
GPIO4. With internal
pull-up, on at reset [PP]
Input
40
GNDH
G
3.3V IO ring power ground (audio SAI,
ResetN, test pins)
41
VDDH
P
3.3V IO ring power supply (audio SAI,
ResetN, test pins)
42
SDO0
B
Radio or audio SAI0 data output
5V tolerant. With
internal pull up, @0V at
reset [PP]
Output
43
SCLK_SCKT
B
SAI0 receive and transmit bit clock
(master or slave with ASRC); SAI1
transmit bit clock
5V tolerant
With internal pull up, on
at reset [PP]
Input
44
LRCK_LRCKT
B
SAI0 receive and transmit left/right clock
(master or slave with ASRC); SAI1
transmit left/right clock
5V tolerant
With internal pull up, on
at reset [PP]
Input
45
TST2_SCKR
B
SAI0 Transmit bit clock; SAI1 receive and
transmit bit clock. Or test selection pin in
test mode
5V tolerant. DSP0
GPIO6. With internal
pull up, on at reset [PP]
Input
46
TST3_LRCKR
B
SAI0 Transmit LeftRight clock; SAI1
Receive and Transmit bit clock. Or Test
selection pin in Test Mode
DSP0 GPIO7. 5V
tolerant. With internal
pull up, on at reset [PP]
Input
47
VDD
P
Digital core power supply
1.8V
48
GND
G
Digital core power ground
49
DBCK0
B
Debug port clock of DSP0 (DBCK0)
DSP0 GPIO. 9. 5V
tolerant. With internal
pull down, on at reset
[PP]
Input
50
DBIN0
B
Debug port data input of DSP0 (DBIN0)
DSP0 GPIO. 11. 5V
tolerant. With internal
pull down, on at reset
[PP]
Input
51
DBRQ0
B
Debug port request of DSP0 (DBRQ0)
DSP0 GPIO. 5V tolerant
With internal pull up, on
at reset [PP]
Input
52
DBOUT0
B
Debug port data output of DSP0
(DBOUT0)
DSP0 GPIO10. 5V
tolerant. With internal
pull up, on at reset [PP]
Input
Table 5.
Pin description (continued)
N°
Name
Type
Description
Notes
After
Reset
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|---|---|
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