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參數(shù)資料
| 型號： | TDA7567PDTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PDSO36 |
| 封裝： | ROHS COMPLIANT, SOP-36 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大小： | 346K |
| 代理商： | TDA7567PDTR |
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TDA7567PD
I2C bus
Doc ID 16903 Rev 1
8
I2C bus
8.1
I2C programming/reading sequences
A correct turn on/off sequence respectful of the diagnostic timings and producing no audible
noises could be as follows (after battery connection):
●
Turn-on: Pin2 > 7V --- 10 ms --- (STANDBY OUT + DIAG ENABLE) --- 500 ms (min) ---
MUTING OUT
●
Turn-off: MUTING IN --- 20 ms --- (DIAG DISABLE + STANDBY IN) --- 10 ms --- PIN2 = 0
●
Car radio installation: Pin2 > 7V --- 10ms DIAG ENABLE (write) --- 200 ms --- I2C read
(repeat until All faults disappear).
●
Offset test: Device in Play (no signal) -- OFFSET ENABLE - 30 ms - I2C reading (repeat
I2C reading until high-offset message disappears).
8.2
I2C bus interface
Data transmission from microprocessor to the TDA7567PD and viceversa takes place
through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).
8.2.1
Data validity
As shown by Figure 16, the data on the SDA line must be stable during the high period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
8.2.2
Start and stop conditions
As shown by Figure 17 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
8.2.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
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