參數(shù)資料
型號： TDA7528
廠商： STMICROELECTRONICS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64
文件頁數(shù)： 36/65頁
文件大小： 610K
代理商： TDA7528
TDA7528
Programming information
Doc ID 13141 Rev 6
5
Programming information
5.1
Address organization
Figure 9.
Address organization
Note:
The power on value of all registers is zero.
Name
No r/w
MSB
6
5
4
3
2
1
LSB
Short reg
0
r/w
x
PWRSTABLEw
ShAGC
ShPLL
ADCen
GPIOen
PWR
ADCctrl
1
r/w
ADCclk
ADCs2
ADCs1
ADCs0
RCenable
ADCautomode
Temp_pwr
GPIOmode
2
r/w
GPO8
GPO7
GPIO6
GPIO5
GPO4
GPO3
GPIO2
GPIO1
AGCmixCtrl
3
r/w
KeyAGCen
FMAGCpwr
AMAGCpwr
Mixout1
Mixout2
Supply
4
r/w
refmode1
refmode0
DivRen
VCCmon_adj1
VCCmon_adj0
En_VCCmon
VDD_korr
VDD_int_ext
DivR1
5
r/w
divr15
divr14
divr13
divr12
divr11
divr10
divr9
divr8
IFAGC
6
r/w
IFAGC_FM_AM
IFAGCthr2
IFAGCthr1
IFAGCthr0
IFsection_pwr
FMAGC
7
r/w
FMthr3
FMthr2
FMthr1
FMthr0
FMAGCmodeC1
FMAGCmodeC0
FMAGCmodeV1
FMAGCmodeV0
FM_AM_Vthr
8
r/w
AMAGCfat
AM2nd_order
Vthr5
Vthr4
Vthr3
Vthr2
Vthr1
Vthr0
MIXalign1
9
r/w
AAfilt1
AAfilt0
Mix_ctrl
IMRF2
IMRF1
IMRF0
MIXalign2
10
r/w
IMRph3
IMRph2
IMRph1
IMRph0
IMRG3
IMRG2
IMRG1
IMRG0
PLLctrl
11
r/w
DZ2
DZ1
DS2
DS1
VCOext
PLLtest2
PLLtest
PLLpwr
PLLctrl2
12
r/w
CompDAC3
CompDAC2
CompDAC1
CompDAC0
CompDACtest2
CompDACtest1
CompDACtest0
CompDACdisable
PLLtest
13
r/w
POL
PFD_D1
PFD_D0
PLLT4
PLLT3
PLLT2
PLLT1
PLLT0
Misc1
14
r/w
AGCtest1
AGCtest0
BalunoutIMP
Ired_Balun
IredH
IredL
VCOMag1
VCOMag0
Misc2
15
r/w
IFbufG2
IFbufG1
IFbufG0
IFbufin
IFbufPWR
RC_test
RCfreq_1
RCfreq_0
AGCtc_A
16
r/w
IFAGCtcAM
IFAGCtcFM
AMtc1
AMtc0
FMtc3
FMtc2
FMtc1
FMtc0
AMAGC_A
17
r/w
AMthr3
AMthr2
AMthr1
AMthr0
AMAGCmodeC1
AMAGCmodeC0
AMAGCmodeV1
AMAGCmodeV0
GPIOm_A
18
r/w
GPO8hl
GPO7hl
GPIO6hl
GPIO5hl
GPO4hl
GPO3hl
GPIO2hl
GPIO1hl
IFCTRL_A
19
r/w
IFin0_Std_IBOC
IFAmpgainA2
IFAmpgainA1
IFAmpgainA0
MixinFM
MixinAM_LPF
MixinFMAM
IFin1_AM_FM
DivV_A
20
r/w
VCO1r
divVA6
divVA0
DivN_A1
21
r/w
divnA20
divnA19
divnA18
divnA17
divnA16
divnA15
divnA14
divnA13
DivN_A2
22
r/w
divnA12
divnA11
divnA10
divnA9
divnA8
divnA7
divnA6
divnA5
DivN_A3
23
r/w
divnA4
divnA3
divnA2
divnA1
divnA0
fracA2
fracA1
fracA0
DivR2_A
24
r/w
divr7
divr6
divr5
divr4
divr3
divr2
divr1
divr0
CPcur_A
25
r/w
CPAh3
CPAh2
CPAh1
CPAl4
CPAl3
CPAl2
CPAl1
CPAl0
DAC1_A
26
r/w
DAC1A8
DAC1A7
DAC1A6
DAC1A5
DAC1A4
DAC1A3
DAC1A2
DAC1A1
DAC2_A
27
r/w
DAC2A8
DAC2A7
DAC2A6
DAC2A5
DAC2A4
DAC2A3
DAC2A2
DAC2A1
PLL_DAC_A
28
r/w
IQselA
VCOsw
CPctrl1
CPctrl0
DAC2A0
DAC2off
DAC1off
AMFilt_A
29
r/w
AMfiltA7
AMfiltA6
AMfiltA5
AMfiltA4
AMfiltA3
AmfiltA2
AMfiltA1
AMfiltA0
Misc3_A
30
r/w
DIVVtest
divnA21
CPAh0
AMLNApwrA
ADCtest_A
31
r/w
IF test
ADC test
ADCDAC5
ADCDAC4
ADCDAC3
ADCDAC2
ADCDAC1
ADCDAC0
AGCtc_B
32
r/w
AMAGC_B
33
r/w
GPIOm_B
34
r/w
IFCTRL_B
35
r/w
DivV_B
36
r/w
DivN_B1
37
r/w
DivN_B2
38
r/w
DivN_B3
39
r/w
DivR2_B
40
r/w
CPcur_B
41
r/w
DAC1_B
42
r/w
DAC2_B
43
r/w
PLL_DAC_B
44
r/w
AMFilt_B
45
r/w
Misc3_B
46
r/w
ADCtest_B
47
r/w
READ_Status
48
r
GPIO6r
GPIO5r
PWR_stable
MaskSet0
MaskSet1
MaskSet2
READ_ADC
49
r
ADCok
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
depends on reception band (FM / MW / SW / …)
to be changed with each frequency change
additional controls, changed indipendent from reception
test registers, not to be changed at all
IF buffer control
ADCstart
this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output
all bytes from 33 to 47 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 31 are valid on the output
initialization registers, to be changed after power on
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