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參數(shù)資料
| 型號： | TDA7511 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 接收器 |
| 英文描述： | AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大小： | 892K |
| 代理商： | TDA7511 |
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TDA7511
The IF-Counter Mode
The IF counter works in 2 modes controlled by IFCM register.
Sampling Timer
A sampling timer to generate the gate signal for the main counter is build with a 14-bit programmable counter
(IRC). In FM mode a 6.25kHz, in AM mode a 1kHz basically signal is generated. This is followed by an asyn-
chronous divider to generate several sampling times.
Intermediate Frequency Main Counter
This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to have
the possibility for an adjust to the frequency of the IF-filter. The counter length is automatic adjusted to the cho-
sen sampling time and the counter mode (FM, AM-UPC).
At the start the counter will be loaded with a defined value which is an equivalent to the divider value
(tSample xfIF).
If a correct frequency is applied to the IF counter frequency input at the end of the sampling time the main
counter is changing its state from 0h to 1FFFFFh.
This is detected by a control logic and an external search stop output is changing from LOW to HIGH. The fre-
quency range inside which a successful count result is adjustable by the EW bits.
tTIM = (IRC + 1) / fOSC
tCNT = (CF + 1697) / fIF
FM mode
tCNT = (CF + 10689) / fIF
AM up conversion mode
Counter result succeeded:
tTIM ≥ tCNT - tERR
tTIM ≤ tCNT + tERR
Counter result failed:
tTIM > tCNT + tERR
tTIM < tCNT - tERR
tTIM = IF timer cycle time
tCNT = IF counter cycle time
tERR = discrimination window (controlled by the EW registers)
The IF counter is only started by inlock information from the PLL part. It is enabled by software (IFENA).
Adjustment of the Measurement Sequence Time
The precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by
programming the control registers EW0 to EW2.
The measurement time per cycle is adjustable by setting the Register IFS0 - IFS2.
Adjust of the Frequency Value
The center frequency of the discrimination window is adjustable by the control register CF0 to CF4.
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