參數(shù)資料
型號: TDA7500
廠商: STMICROELECTRONICS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: TQFP-100
文件頁數(shù): 36/40頁
文件大?。?/td> 391K
代理商: TDA7500
5/40
TDA7500
31
DSRA<5>
I/O
DSP SRAM Data Lines<5> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 5.
32
DSRA<4>
I/O
DSP SRAM Data Lines<4> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 4.
33
DSRA<3>
I/O
DSP SRAM Data Lines<3> (Input/Output)/DSP DRAM Data
Line<3>(Input/Output). This pin act as the EMI data line 3 in
both SRAM Mode and DRAM Mode.
34
DSRA<2>
I/O
DSP SRAM Data Lines<2> (Input/Output)/DSP DRAM Data
Line<2>(Input/Output). This pin act as the EMI data line 2 in
both SRAM Mode and DRAM Mode.
35
DSRA<1>
I/O
DSP SRAM Data Lines<1> (Input/Output)/DSP DRAM Data
Line<1>(Input/Output). This pin act as the EMI data line 1 in
both SRAM Mode and DRAM Mode.
36
DSRA<0>
I/O
DSP SRAM Data Lines<0> (Input/Output)/DSP DRAM Data
Line<0>(Input/Output). This pin act as the EMI data line 0 in
both SRAM Mode and DRAM Mode.
37
SRA<0>
O
DSP SRAM Address Line<0> (Output)/DSP DRAM Address
Line<0> (Output). This pin acts as the EMI address line 0 in both
SRAM Mode and DRAM Mode
38
SRA<1>
O
DSP SRAM Address Line<1> (Output)/DSP DRAM Address
Line<1> (Output). This pin acts as the EMI address line 1 in both
SRAM Mode and DRAM Mode
39
SRA<2>
O
DSP SRAM Address Line<2> (Output)/DSP DRAM Address
Line<2> (Output). This pin acts as the EMI address line 2 in both
SRAM Mode and DRAM Mode
40
SRA<3>
O
DSP SRAM Address Line<3> (Output)/DSP DRAM Address
Line<3> (Output). This pin acts as the EMI address line 3 in both
SRAM Mode and DRAM Mode
41
SRA<4>
O
DSP SRAM Address Line<4> (Output)/DSP DRAM Address
Line<4> (Output). This pin acts as the EMI address line 4 in both
SRAM Mode and DRAM Mode
42
SRA<5>
O
DSP SRAM Address Line<5> (Output)/DSP DRAM Address
Line<5> (Output). This pin acts as the EMI address line 5 in both
SRAM Mode and DRAM Mode
43
SRA<6>
O
DSP SRAM Address Line<6> (Output)/DSP DRAM Address
Line<6> (Output). This pin acts as the EMI address line 6 in both
SRAM Mode and DRAM Mode
44
SRA<7>
O
DSP SRAM Address Line<7> (Output)/DSP DRAM Address
Line<7> (Output). This pin acts as the EMI address line 7 in both
SRAM Mode and DRAM Mode
45
SRA<8>
O
DSP SRAM Address Line<8> (Output)/DSP DRAM Address
Line<8> (Output). This pin acts as the EMI address line 8 in both
SRAM Mode and DRAM Mode
Name
Type
Description
PIN DESCRIPTION (continued)
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