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參數(shù)資料
| 型號(hào)： | TDA7429L |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP42 |
| 封裝： | 0.600 INCH, SDIP-42 |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | TDA7429L |
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TDA7429L
4
SOFTWARE SPECIFICATION
4.1 Interface Protocol
The interface protocol comprises:
■
A start condition (S)
■
A chip address byte, containing the TDA7429L address
■
A subaddress bytes
■
A sequence of data (N byte + achnowledge)
■
A stop condition (P)
Figure 8.
5
EXAMPLES
5.1 No Incremental Bus
The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incre-
mental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
Figure 9.
5.2 Incremental Bus
The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental
bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2
concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
Figure 10.
S
1
0
A
0
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D95AU226A
B
DATA
SUBADDRESS
DATA 1 to DATA n
S
1
0
A
0
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D95AU306
0
D3
SUBADDRESS
DATA
X
D2 D1 D0
S
1
0
A
0
ACK
DATA
ACK
P
MSB
LSB
MSB
LSB
MSB
LSB
CHIP ADDRESS
D95AU307
1
D3
SUBADDRESS
DATA 1 to DATA n
X
D2 D1 D0
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