參數(shù)資料
型號(hào): TDA7427AD1TR
廠商: STMICROELECTRONICS
元件分類(lèi): PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 200 MHz, PDSO28
封裝: SO-28
文件頁(yè)數(shù): 19/22頁(yè)
文件大?。?/td> 444K
代理商: TDA7427AD1TR
GENERAL DESCRIPTION
This circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning sys-
tems. Only a VCO is required to build a complete
PLL system. For auto search/stop operation an IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stage configuration. The first stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit pro-
grammable counter.
For LW and MW application, a 16-bit programma-
ble counter is available.
The circuit receives the scaling factors for the pro-
grammable counters and the values of the refer-
ence frequencies via a I
2C bus interface.
The reference frequency is generated by an inter-
nal XTAL oscillator followed by the reference di-
vider. The device can operate with XTAL oscilla-
tor between 4 and 13MHz either in master mode
and in slave mode.
The reference and step frequencies are free se-
lectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.
Values of the current sources are programmable
by 6 bits also received via the I
2C bus.
To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the cur-
rent values of the charge/pump generator.
IF COUNTER SYSTEM
Two separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuring cycle times.
The tolerance of the accepted count value is ad-
justable, to reach an optimum compromise for
search speed and precision of the evaluation.
For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter toler-
ance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-con-
version) with 1KHz steps is available.
PLL FREQUENCY SYNTHESIZER
Input Amplifiers
The signals applied on AM and FM inputs are am-
plified to get a logic level in order to drive the fre-
quency dividers.
The typical input impedance for FM and AM in-
puts is 4k
.
MSB
LSB
FUNCTION
SUBAD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PLL CHARGE PUMP
00H
LPIN1/2
CURRH
B1
B0
A3
A2
A1
A0
PLL COUNTER
01H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PLL COUNTER
02H
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PLL REF COUNTER
03H
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
PLL REF COUNTER
04H
RC15
RC14
RC13
RC12
RC11
RC10
RC9
RC8
PLL LOCK DETECT
05H
LDENA
INLOCK
D3
D2
D1
D0
PM1
PM0
IFC REF COUNTER
06H
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
IFC REF COUNTER
07H
IFCM1
IFCM0
IRC13
IRC12
IRC11
IRC10
IRC9
IRC8
IFC CONTROL
08H
IFENA
-
EW2
EW1
EW0
IFC CONTROL
09H
IFS2
IFS1
IFS0
CF4
CF3
CF2
CF1
CF0
OSC ADJUST
0AH
-
OSC4
OSC3
OSC2
OSC1
OSC0
PORT EXTENSION
0BH
-
DOUT3
DOUT4
DOUT5
DOUT6
DOUT2
DOUT1
Table 1. Address Organization
TDA7427A
6/21
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