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參數(shù)資料
| 型號(hào)： | TDA7410NDTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO20 |
| 封裝： | LEAD FREE, SOP-20 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 412K |
| 代理商： | TDA7410NDTR |
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Description of stereodecoder
TDA7410ND
6.4
PLL and pilot tone detector
The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a
correct demodulation. The included detector enables the demodulation if the pilot tone
reaches the selected pilottone threshold VPTHST. Two different thresholds are available.
The detector output (signal STEREO, see block diagram) can be checked by reading the
status byte of the TDA7410ND via I2C bus.
6.5
Fieldstrength control
The fieldstrength input is used to control the highcut and the stereoblend function. In
addition the signal can be also used to control the noiseblanker thresholds.
6.6
LEVEL input and gain
To suppress undesired high frequency modulation on the highcut and stereoblend function
the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1st order RC
lowpass at 53kHz (working as anti-aliasing filter) and a 1st order switched capacitor lowpass
at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal
internally to different IF. The gain is widely programmable in 16 steps from 0dB to 10dB
(step = 0.67dB).
6.7
Stereoblend control
The stereoblend control block converts the internal LEVEL voltage (LEVEL INTERN) into an
demodulator
compatible analog signal which is used to control the channel separation between 0dB and
the maximum separation. Internally this control range has a fixed upper limit which is the
internal reference voltage REF5V. The lower limit can be programmed to be 33%, 42%, 50%
Figure 13.
Internal stereoblend characteristics
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
012
LEVELINTERN [V]
CS [dB]
345
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