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參數(shù)資料
| 型號： | TDA7403DTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | SO-20 |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 232K |
| 代理商： | TDA7403DTR |
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VTR
Trigger Threshold
0) 1)
meas. with VPEAK = 0.9V
NBT = 111
30
mVOP
NBT = 110
35
mVOP
NBT = 101
40
mVOP
NBT = 100
45
mVOP
NBT = 011
50
mVOP
NBT = 010
55
mVOP
NBT = 001
60
mVOP
NBT = 000
65
mVOP
VTRNOISE
Noise Controlled Trigger
Threshold
2)
meas. with VPEAK = 1.5V
NCT = 00
260
mVOP
NCT = 01
220
mVOP
NCT = 10
180
mVOP
NCT = 11
140
mVOP
VRECT
Rectifier Voltage
VMPX = 0mV
0.9
V
VMPX = 50mV; f = 150KHz
1.7
V
VMPX = 100mV; f = 150KHz
2.5
V
VRECT DEV
deviation dependent
rectifier Voltage
3)
means. with
VMPX = 800mV
(75KHz dev.)
OVD = 11
0.9(off)
VOP
OVD = 10
1.2
VOP
OVD = 01
2.0
VOP
OVD = 00
2.8
VOP
VRECT FS
Fieldstrength Controlled
Rectifier Voltage
4)
means. with
VMPX = 0mV
VLEVEL << VSBL
(fully mono)
FSC = 11
0.9(off)
V
FSC = 10
1.3
V
FSC = 01
1.8
V
FSC = 00
2.3
V
0) All thresholds are measured using a pulse with TR = 2
s, THIGH = 2 s and TF = 10 s.
1) NBT represents the Noiseblanker-Byte bits D2; D0 for the noise blanker trigger threshold
2) NAT represents the Noiseblanker-Byte bit pair D4,D3 for the noise controlled trigger adjustment
3) OVD represents the Noiseblanker-Byte bit pair D7,D6 for the over deviation detector
4) FSC represents the Fieldstrength-Byte bit pair D1,D0 for the fieldstrength control
VOP
VIN
DC
TR
THIGH
TF
Time
D97AU636
NOISE BLANKER PART
internal 2nd order 140kHz high pass filter
programmable trigger threshold
additional circuits for trigger adjustment (devia-
tion, field-strenght)
very low offset current during hold time
four selectable pulse suppression times
TDA7403
11/25
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