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參數(shù)資料
| 型號(hào)： | TDA7342 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 316K |
| 代理商： | TDA7342 |
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Figure 4: Timing Diagram of I
2CBUS
Figure 3: Data Validity on the I
2CBUS
I
2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7342 and viceversa takes place thru the 2
wires I
2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 5: Acknowledge on the I
2CBUS
TDA7342
7/14
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| TDA7344S | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP42 |
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| TDA7346 | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| TDA7346D | SPECIALTY CONSUMER CIRCUIT, PDIP20 |
相關(guān)代理商/技術(shù)參數(shù) |
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| TDA7342_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Digitally controlled audio processor |
| TDA7342EQ2N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Digitally controlled audio processor |
| TDA7342EQ2NTR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Digitally controlled audio processor |
| TDA7342N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Digitally controlled audio processor |
| TDA7342NTR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Digitally controlled audio processor |
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