參數(shù)資料
型號(hào): TDA7333
廠商: STMICROELECTRONICS
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO16
封裝: 4.40 MM, TSSOP-16
文件頁(yè)數(shù): 9/21頁(yè)
文件大?。?/td> 677K
代理商: TDA7333
Obsolete
Product(s)
- Obsolete
Product(s)
17/21
TDA7333
8.3 SPI mode
Figure 16. SPI data transfer
This interface consists of four lines. A serial data input (DATAIN), a serial data output (DATAOUT), a chip select
input (CSN) and a bit clock input (CLK).
The chip select input signals the begin and end of the data transfer. If the data transfer starts, at each
bit clock one bit is clocked out via the serial data output and one bit is clocked in via the serial data input.
When chip enable signals the begin of the data transfer the internal 64 bits shift register is updated with the cur-
rent registers content of the V324.
When chip enable signals the end of the data transfer the registers with write access can be updated with the
bits which have been last shifted in.
The last byte on DATAIN input is always rds_int[7:0] and the former last one is rds_bd_ctrl[7:0]. In other words,
the master has to take in account the amount of bytes transmitted when intending to perform a write operation
so that the last two bytes sent on DATAIN are rds_bd_ctrl[7:0] and rds_int[7:0].
If the update of both rds_int and rds_bd_ctrl registers is actually taking place depends on the MSB of rds_int,
i.e. rds_int[7] = 0 - no update, rds_int[7] = 1 update of both registers.
Hereafter you can find typical read/write access in spi mode :
Figure 17. write rds_int and rds_bd_ctrl registers in spi mode,reading RDS data and related flags
CSN
DATAIN
DATAOUT
CLK
rds_int[0]
rds_int[1]
2
64
63
8
7
6
5
4
3
1
rds_int[7]
testreg[0]
rds_int[6]
rds_int[0]
rds_int[1]
rds_int[2]
rds_int[3]
rds_int[4]
rds_int[5]
testreg[1]
shift of DATAIN
in shiftregister
update of
shiftregister with
registers content
update of registers
with shiftregister
content if requested
tcsu
tsu
th
todv toh
tcsh
tcl tch
td
CSN
DATAIN
DATAOUT
CLK
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
rds_bd_h[7:0]
rds_bd_l[7:0]
{1,rds_int[6:0]}
rds_bd_ctrl[7:0]
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