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參數(shù)資料
| 型號： | TDA7326D |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 140 MHz, PDSO16 |
| 封裝： | SO-16 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 1133K |
| 代理商： | TDA7326D |
3.3 DIVIDER FROM VCO FREQUENCY TO
REFERENCE FREQUENCY
This divider provides a low frequency fSYN which
is phase compared with the reference frequency
fREF.
3.4 OPERATING MODE
Four operating modes are available:
- FM mode,
- AM swallow mode,
- AM direct mode,
- Standby mode
They are user programmable with the SWR/DIR
and AM/FM bits in the byte 2.
Standby mode: all functions are stopped. This al-
lows low current consumption without lost of infor-
mation in all register, it is activated by forcing bit 0
(AM/FM) and bit 1 (SWM/DIR) both at zero value.
3.4.1 FM and AM (SW) Operation (Swallow
Mode)
The FM or AM signal is applied to a four
modulus: 32/33/64/65 high speed prescaler,
which is controlled by a 6 bit divider ’A’.This
divider is controlled by the 6 bit SC register.
In parallel the output of the prescaler is con-
nected to a 8 bit divider ’B’. This divider is
controlled by the 8 bit PC register. For FM
mode with 25kHz reference frequency opera-
tion, the divider A is a 5 bit divider. The high
speed prescaler is working in : 32/33 dividing
mode. Bit 6 of the SC register has to be kept
to "0".
Dividing range calculation :
For FM mode with 12.5kHz reference fre-
quency and SW swallow mode operation :
fVCO = [ 65
A1 + (B1 + 1 - A1) 64 ] . fREF or
Important : For correct operation B
≥ 64 and B
≥ A.
At FM mode with 25kHz reference frequency :
fVCO = [ 33
A2 + (B2 + 1 - A2) 32 ] fREF
Important: For correct operation B
≥ 32 and B
≥ A.
A and B are variable values of the dividers.
To keep the actual tuning frequency after a
modification of the reference frequency, the
values of the dividers have to be modified in
the following way.
Switching from 25kHz to 12.5kHz reference
frequency : B1 = B2, A1 = A2
2
Switching from 12.5kHz to 25kHz reference
frequency:
B2 = B1, A2
=
A1
2
and A2
= (
A1
+ 1)
2
for odd values A1.
The AM signal is directly applied to the 14 bit
static divider ’C’. This divider is controlled by
both SC and PC registers.
Dividing range:
PREDIVIDER
R
OSC IN
REGISTER
SC5 .. SC0
COUNTER
A
PREDIVIDER
M/M+1
AM IN
FM IN
REGISTER
PC7 .. PC0
COUNTER
B
PD
fref
fsyn
D94AU101
Figure 2: FM and AM (SW) operation (swallow mode)
MODE SECTION
SWM/DIR
AM/FM
STAND-BY
0
FM
1
0
AM SWALLOW
0
1
AM DIRECT
1
fVCO = (64
B1 + A1 + 64) fREF
fVCO = (32
B2 + A2 + 32) fREF
fVCO = (C + 1)
fREF
TDA7326
6/16
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