參數資料
型號: TDA7317
廠商: STMICROELECTRONICS
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), EQUALIZER CIRCUIT, PDIP30
封裝: 0.400 INCH, SDIP-30
文件頁數: 7/12頁
文件大?。?/td> 826K
代理商: TDA7317
DEVICE DESCRIPTION
The TDA7317 is a five bands, digitally controlled
stereo Graphic Equalizer.
The device is intended for high quality audio ap-
plication in Hi-Fi, TV and car radio systems where
feature like low noise and THD are key factors. A
mixed Bipolar Cmos Technology allows:
Cmos analog switches for pop free commuta-
tions, high frequency op.amp. (GWB = 10MHz)
and high linearity polisilicon resistor for THD =
0.01 (at Vin = 1Vrms) and a S/N ratio of 102dB.
The internal Block Diagram is shown on page 1.
The first stage is a volume control. The control
range is 0 to -17.625dB with 0.375dBstep.
The very high resolution (0.375dB step) allows
the implementation of closed loop amplitude con-
trol system completely free from any acustical ef-
fect (stepping variation and pumping effect).
The volume control is followed by a serial five
bands equalizer. Each filtering cell is the biquad
cell shown in fig. 1
The internal resistor string is fixing the boost/cut
value while the buffer makes the Q (quality factor)
and central frequency, set by external compo-
nents, fully indipendent from the internal resistors.
Each filtering cell is realized using only 4 external
components (2 capacitors and 2 resistors) allow-
ing a flexible selection of centre frequency fo, Q
factor and gain. Here below the basic formulae
and the key features of each band pass filter are
reported:
fo = center frequency
Gv = gain/loss at the center frequency fo
Gv = 20log(Av)
Q
=
fo
f2
f1
where f2, f1 = 3dB Bandwidth limits.
Av
= (
R2
C2 ) + (R2 C1 )
+ (R1 C1 )
(R2 C1 ) + (R2 C2 )
Q
= √
(R1
C1 R2 C2 )
(R2 C1 ) + (R2 C2 )
fo
=
1
2
π √
(R1 R2 C1
C2)
If C1 is fixed, then:
C2
=
Q
2
Av
1 Q2
C1
R2
=
1
2
π C1 fo (
Av
1 ) Q
(Av 1
Q2)
R1
=
(Av 1)2
Av
1
Q2
R2
Likewise, the components’values can be deter-
mined by fixing one of the other three parameters.
Referring to fig. 1 the suggested R2 value should
be higher than 2K
in order to have a good THD
(internal op. amp. current limit).
Viceversa the R1 value should be equal or lower
than 51K
in order to keep the "click"(DC step)
very low.
A typical application is shown by fig. 2
Fig. 1
TDA7317
4/12
相關PDF資料
PDF描述
TDA7318 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP28
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TDA7326 PLL FREQUENCY SYNTHESIZER, 140 MHz, PDIP16
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相關代理商/技術參數
參數描述
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