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參數(shù)資料
| 型號(hào)： | TDA7309D013TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO20 |
| 封裝： | SO-20 |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | TDA7309D013TR |
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TDA7309
6/14
3I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires I2C
BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must
be connected).
3.1 Data Validity
As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig. 16 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
3.4 Acknowledge
The master (
P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
17). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the
P can use a simplier transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data. This approach of
course is less protected from misworking and decreases the noise immunity.
Figure 15. Data Validity on the I2CBUS
Figure 16. Timing Diagram of I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I2CBUS
STOP
D99AU1032
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| TDA7311T | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PQFP44 |
| TDA7311 | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP40 |
| TDA7312 | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP30 |
| TDA7313N | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP28 |
| TDA7313ND | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA7310 | 功能描述:音頻 DSP Serial Audio Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TDA7311 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL BUS CONTROLLED AUDIO PROCESSOR |
| TDA7312 | 功能描述:音頻 DSP Digital Audio Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TDA7313 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS |
| TDA7313D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS |
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