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參數(shù)資料
| 型號(hào)： | TDA7309 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDIP20 |
| 封裝： | DIP-20 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 225K |
| 代理商： | TDA7309 |
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TDA7309
Figure 17. Acknowledge on the I2CBUS
Table 6. SDA, SCL I2CBUS Timing
All values referred to VIH min. and VIL max. levels
(*) Must be guaranteed by the I2C BUS master.
Figure 18. Definition of Timing on the I2C-bus
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSCL
SCL clock frequency
0
400
kHz
tBUF
Bus free time between a STOP and START condition
1.3
s
tHD:STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
0.6
s
tLOW
LOW period of the SCL clock
1.3
s
tHIGH
HIGH period of the SCL clock
0.6
s
tSU:STA
Set-up time for a repeated START condition
0.6
s
tHD:DA
Data hold time
0.300
s
tSU:DAT
Data set-up time
100
ns
tR
Rise time of both SDA and SCL signals
20
300
ns (*)
tF
Fall time of both SDA and SCL signals
20
300
ns (*)
tSU:STO
Set-up time for STOP condition
0.6
s
SCL
1
MSB
23789
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
SDA
SCL
tBUF
P
S
tHD;STA
tLOW
tR
tF
tHD;DAT
tSU;DAT
tHIGH
tF
Sr
P
tSU;STA
tHD;STA
tSP
tSU;STO
D95AU314
P = STOP
S = START
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