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| 型號(hào)： | TDA6501 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5 V mixer/oscillator and synthesizer for PAL and NTSC standards |
| 中文描述： | 5 V型混合機(jī)/振蕩器和合成器PAL和NTSC制式標(biāo)準(zhǔn) |
| 文件頁數(shù)： | 9/37頁 |
| 文件大小： | 223K |
| 代理商： | TDA6501 |
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9397 750 15057
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 14 June 2005
9 of 37
Philips Semiconductors
TDA6500; TDA6501
5 V mixer/oscillator and synthesizer for PAL and NTSC standards
7.2.2
Read mode
Data can be read from the device by setting the R/W bit to logic 1. The data read format is
shown in
Table 11
. After the slave address has been recognized, the device generates an
acknowledge pulse and the first data byte (status byte) is transferred on the SDA line with
the MSB first. Data is valid on the SDA line during a HIGH-level of the SCL clock signal.
A second data byte can be read from the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End of transmission will occur if no
master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is
detected by the device (end of a read sequence).
Control of the loop is made possible with the in-lock flag (FL) which indicates when the
loop is locked (FL = 1).
The internal AGC status is available from the AGC bit. AGC = 1 indicates when the
selected take-over point is reached.
A built-in ADC is available on the P6/ADC pin. The ADC can be used to apply AFC
information to the microcontroller from the IF section of the tuner. The relationship
between the voltage applied to the ADC input and the A2, A1 and A0 bits is given in
Table 13
.
[1]
MSB is transmitted first.
Table 11:
Name
Read data format
Byte
Bit
MSB
[1]
1
POR
Ack
LSB
R/W = 1 A
A0
Address byte
Status byte
ADB
SB
1
FL
0
1
0
1
0
AGC
MA1
A2
MA0
A1
-
Table 12:
Symbol
A
MA1 and MA0
R/W
POR
Description of bits shown in
Table 11
Description
acknowledge
programmable address bits; see
Table 7
logic 1 for read mode
power-on reset flag
POR = 0, normal operation
POR = 1, power-on state
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
internal AGC flag
AGC = 0, internal AGC not active
AGC = 1, internal AGC is active; level below 3 V
A2, A1 and A0
digital output of the 5-level ADC; see
Table 13
FL
AGC
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